Advertisement
"
Bit
Bump
" Offset ( Sub
-
frame offset
) :
The " Bit
Bump "
Offset
(
also known as Sub
-
frame Offset ) is
calculated
by
the built
-
in
synchronizer using the phase
relationship
of the
playback
time code
sync pulse
to the
external reference time code
sync
pulse
,
offset
,
only
the
phase
of the time code
signals
(
playback and
external reference ) is used in
the
calculation
.
For
example
,
in the
previous explanation the
offset calculation was 2
seconds and 22 frames
.
If this offset of 2 seconds and 22
frames is not
exactly
correct
,
an
additional
sub
-
frame offset
( " Bit
Bump
" ) can be added to the calculation
.
This is
accomplished by storing
the value (
00
-
79
) of the sub -
frame
offset into
storage register
#
98
( in addition to the value
previously
stored in
register
#
00 )
.
After the
storage
of the
desired value into
register
#
98
,
the built
-
in
synchronizer
will offset the
phase relationship
of the playback time code
sync
to the external time code reference
.
This offset is
done in l / 80 th of a frame increments in either the
positive
or negative
direction
.
This feature allows the
APR
-
5003
/
5003 V
to offset the synchronization with 416
microsecond
accuracy
.
With this form of
APR
-
5003
/
5003 V
Built
-
in
Synchronizer Operation
4.2
.
3.1
The built
-
in
synchronizer
is available in the
APR
-
5003 V
model
only
.
The
synchronizer
feature is facilitated
by
the
Z
-
8002
microprocessor
circuit and software
program
of the
APR
-
5003
V CPU board and
support circuitry
.
To
fully
understand the
operation
of the
synchronizer
circuitry
in the APR
-
5003 V
,
two commonly
used
operation
sequences
will be
explained
.
The
examples
that will be
discussed
are as shown below
.
For these
examples
,
refer to
the
APR
-
5003 V time code
signal
flow
diagram
in
Figure
4 -
2
.
4.2
.
4
APR
-
5003 V
Chase
Synchronized
to an external LTC
source
.
4.2
.
5
APR
-
5003
V Chase
Synchronized
to an external VITC
source
.
4.2
.
4
APR
-
5003 V Chase
Synchronized
to an External LTC Source
For this
example
,
it will be assumed that the
APR
-
5003
V will
be
synchronizing
( without an offset ) to an external
Longitudinal Time
Code ( LTC ) source
,
source and the
tape
time code are assumed to be SMPTE NDF
.
In this
example
(
as
in all
of the
examples
in this
section )
,
the CPU board will be
performing
the
synchronization
of the
APR
-
5003 V
.
utilizing a
Z
-
8030 (
Serial Communications Controller )
.
The external time code
This is
accomplished by
the
Z
-
8002 circuit
4
-
8
Advertisement
