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In
the R E C O R D mode the
s i g n a l
to be recorded is directed t o
the Record Level
D i g i t a l l y
Controlled Resistor (
DCR
)
•
This
section of the C N L / TCC card controls the a m p l i t u d e of the
s i g n a l
level
t o
be recorded a n d the
Record
E Q
b y r e a d i n g
the
8
-
bit data from the CPU board
.
A buffer
s t a g e s e p a r a t e s
these t w o
s t a g e s
.
T h e Record
S e c o n d a r y
Feed Forward and
Record
S e c o n d a r y
Feedback
a r e s e p a r a t e d b y a
buffer
s t a g e
and
control the Record
s i g n a l c o m p e n s a t i o n
.
T h e s e
c o m p e n s a t i o n
functions
a r e p e r f o r m e d b y s i m p l e s w i t c h i n g
networks that
enter different
combinations of
c a p a c i t o r s into the
filter
network
.
T h e
selection of what combination is
used is
determined
b y
the audio data from the CPU
.
T h e
e i g h t
control
data bits
a r e
divided into two
,
four bit data lines
.
T h e
u p p e r
four bits a r e used for Feed Forward
,
and the lower four
bits a r e used for Feedback control
.
T h e
o u t p u t
of this
s e c t i o n of the CNL / T C C card is the Record D r i v e
s i g n a l
.
T h e
Record Drive signal exits t h e C N L / TCC card ( via c o n n e c t o r
CNJ 211
-
N
p i n 8 A
) to tha ADM board
,
where the
s i g n a l is
routed
to the F r o n t
End Transformer ( FEX ) board via
p i n 6 of
CNJ 213
-
N
.
T h e
FEX board is the
p o i n t
of combination for the Record
D r i v e
s i g n a l
and the B i a s s i g n a l
.
It is here
(
at the
FEX
board ) that t h e final
r e l a y
switch
is
thrown
,
thus
c o n n e c t i n g
the entire Record circuit from the
LINE INPUT
connectors to
the RECORD / SYNCHRONOUS PB head
.
o
T h e B i a s and Erase
s i g n a l s o r i g i n a t e o n
the M a s t e r ( M S T )
card
.
These
s i g n a l s
( Bias and Erase )
a r e
routed from the MST
card (
a s
clock
s i g n a l s
)
to the CNL / T C C cards v i a the ADM
board
.
T h e Bias and Erase clock
s i g n a l s
enter the CNL / T C C
card (
s ) at
CNJ 211
-
N
p i n s 3 3
A ( Bias ) and 3 3 B ( Erase )
.
These
s i g n a l s a r e
processed t h r o u g h the R a m p Generator w h e r e the
t i m i n g
for
R a m p U p
and
R a m p
Down is determined
.
T h e Bias and
Erase
s i g n a l s a r e
then s e n t t o
a current m u l t i p l i e r s t a g e
.
T h e current
m u l t i p l i e r s t a g e h o u s e s t h e ON
-
B O A R D
a d j u s t m e n t
of the B i a s and Erase
s i g n a l s
.
A
d i g i t a l
switch controls the
o u p u t
of the current
m u l t i p l i e r
,
thus
c o n t r o l l i n g
the
i n p u t
of the next
s t a g e
,
the final Erase and Bias drive circuits
.
T h e Bias a n d
Erase driver circuits
a m p l i f y the s i g n a l t o
the
final level for the Bias a n d Erase heads
.
Both
t h e Bias and
Erase
s i g n a l s
are
o u p u t
from the CNL /
T C C
card and
routed to
the
FEX
board via the
ADM
a n d
the shielded cable
.
U p o n
arrival
at t h e
FEX
board
,
t h e B i a s s i g n a l is
combined with
the R e c o r d D r i v e
s i g n a l
and directed t o the RECORD / S Y N C head
.
T h e Erase s i g n a l is routed t o the 1
: 10
s t e p
-
u p
transformer
.
T h e
o u t p u t
of the transformer is directed to the ERASE head
.
5
-
2
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