Siemens SIMATIC S5 Manual page 122

Ip 265 high speed sub control
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IP 265
Example: Critical signal chart due to latching language element (Set/Reset operation) in a segment
of the IP 265 user program
Table 9-7.
CSF: "Critical signal chart"
&
I 0.0
I 0.1
&
I 0.0
I 0.2
: Connecting line in which delay is to be inserted
Purpose of the partial segment (Table 9-7):
The counter is always to count up when one of the two "AND" conditions is true. If both of the
"AND" conditions are true at one and the same instant, or if neither of the "AND" conditions is
true, no counting pulse is to be generated at counting input CU (prerequisite: the RS flipflop's
Reset input (R) is "0").
Development of the critical signal chart:
The information presented in Section 4-1 of the Product Manual has shown us that a latching
language element (such as an RS flipflop) in a segment generates an additional delay of 7.8 µs.
In our example, this means that, should the conditions for both "AND" operations be true at the
same time, the result of the first "AND" operation would be incorporated into the "XOR"
operation 7.8 µs after the result of the second "AND" operation. For a period of 7.8 µs,
therefore, it would be as though the results of the two "AND" operations were not identical,
even though a positive signal change would take place at the same instant at inputs I 0.1 and
I 0.2 ( Table 9-7: Timing diagram). Erroneously, a brief positive edge would be generated at
the counter input.
Averting the critical signal chart:
Placing the "Delay" language element in the second circuit of the segment would synchronize
the signal via the RS flipflop.
EWA 4NEB 812 6130-02a
Example: Using the "Delay" Language Element
S
XOR
R
Q
Programming the IP 265 with COM 265
"Critical signal chart"
Signal states
1
0
1
0
1
CU/D
0
> CU
1
> CD
0
CV
> S BI
1
t:
R
Q
Timing diagram:
I 0.0
I 0.1
I 0.2
Critical signal
chart
CU
Time
t
in ms
kHz=7.8 µs
/
128
9-17

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