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5.2.1. Vector Table Offset Address (VTOR)
The CPU core provides the vector table offset register to set the offset (start) address of the vector
table in which interrupt vectors are programmed. "VTOR" described in Table 5.2.1 means the value set
to this register. After an initial reset, VTOR is set to address 0x0. Therefore, even when the vector table
location is changed, it is necessary that at least the reset vector be written to this address. For more
information on VTOR, refer to the "Cortex
5.2.2. Priority of Interrupts
The priorities of SVCall, PendSV, and SysTick are configurable to the desired levels using the System
Handler Priority Registers (SHPR2 and SHPR3). The priorities of the interrupt number 16 or later are
configurable to the desired levels using the Interrupt Priority Registers (NVIC_IPR0–7). The priority value
can be set within a range of 0 to 192 (a lower value has a higher priority). The priorities of reset, NMI, and
HardFault are fixed at the predefined values. For more information, refer to the "Cortex
Reference Manual."
5.3. Peripheral Circuit Interrupt Control
The peripheral circuit that generates interrupts includes an interrupt enable bit and an interrupt flag for
each interrupt cause.
Interrupt flag:
Interrupt enable bit:
For specific information on causes of interrupts, interrupt flags, and interrupt enable bits, refer to the
respective peripheral circuit descriptions.
Note:
To prevent occurrence of unnecessary interrupts, the corresponding interrupt flag should be
cleared before setting the interrupt enable bit to 1 (interrupt enabled) and before terminating the
interrupt handler routine.
5.4. NMI
The watchdog timer embedded in this IC can generate a non-maskable interrupt (NMI). This interrupt
takes precedence over other interrupts and is unconditionally accepted by the CPU.
For detailed information on generating NMI, refer to the "Watchdog Timer" chapter.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
-M0+ Technical Reference Manual."
®
The flag is set to 1 when the interrupt cause occurs. The clear condition
depends on the peripheral circuit.
By setting this bit to 1 (interrupt enabled), an interrupt request will be sent to
the CPU core when the interrupt flag is set to 1. When this bit is set to 0
(interrupt disabled), no interrupt request will be sent to the CPU core even if
the interrupt flag is set to 1. An interrupt request is also sent to the CPU core if
the status is changed to interrupt enabled when the interrupt flag is 1.
Seiko Epson Corporation
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