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12.6. Control Registers
T16 Ch.n Clock Control Register
Register name
Bit
T16_nCLK
15–9
8
7–4
3–2
1–0
Bits 15–9
Reserved
Bit 8
DBRUN
This bit sets whether the T16 Ch.n operating clock is supplied during debugging or not.
1 (R/W): Clock supplied during debugging
0 (R/W): No clock supplied during debugging
Bits 7–4
CLKDIV[3:0]
These bits select the division ratio of the T16 Ch.n operating clock (counter clock).
Bits 3–2
Reserved
Bits 1–0
CLKSRC[1:0]
These bits select the clock source of T16 Ch.n.
T16_nCLK.
CLKDIV[3:0] bits
0xe
0xd
0xc
0xb
0xa
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
(Note 1) The oscillation circuits/external input that are not supported in this IC cannot be
selected as the clock source.
(Note 2) When the T16_nCLK.CLKSRC[1:0] bits are set to 0x3, EXCLm is selected for the channel
with an event counter function or EXOSC is selected for other channels.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Bit name
Initial
–
0x00
DBRUN
CLKDIV[3:0]
–
CLKSRC[1:0]
Table 12.6.1 Clock Source and Division Ratio Settings
0x0
IOSC
0xf
1/32,768
1/16,384
1/8,192
1/4,096
1/2,048
1/1,024
1/512
1/256
1/128
1/64
1/32
1/16
1/8
1/4
1/2
1/1
Seiko Epson Corporation
Reset
R/W
–
R
0
H0
R/W
0x0
H0
R/W
0x0
–
R
0x0
H0
R/W
T16_nCLK.CLKSRC[1:0] bits
0x1
0x2
OSC1
OSC3
1/1
1/32,768
1/16,384
1/8,192
1/4,096
1/2,048
1/1,024
1/512
1/256
1/256
1/128
1/128
1/64
1/64
1/32
1/32
1/16
1/16
1/8
1/8
1/4
1/4
1/2
1/2
1/1
1/1
Remarks
–
0x3
EXOSC/EXCLm
1/1
12-5
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