Internal clock
VDD
MD10 to MD0
CKIO
Notes: 1. Oscillation settling time when on-chip resonator is used
2. PLL2 operating
Standby
Internal
clock
or
CKIO
Notes: 1. Oscillation settling time when on-chip resonator is used
2. PLL2 operating
Figure 23.6 Standby Return Oscillation Settling Time (Return by
Rev. 3.0, 04/02, page 958 of 1064
V
min
DD
t
OSC1
t
Figure 23.5 Power-On Oscillation Settling Time
t
RESW
OSCMD
t
TRSTRH
t
OSC2
Stable oscillation
t
MDRH
Stable oscillation
t
RESW
or
)