Burst Rom Interface; Overview; Basic Timing - Hitachi H8S/2646 Hardware Manual

7.5

Burst ROM Interface

7.5.1

Overview

In this LSI, the area 0 external space can be set as burst ROM space and burst ROM interfacing
performed. Burst ROM space interfacing allows 16-bit ROM capable of burst access to be
accessed at high-speed.
The BRSTRM bit of BCRH sets area 0 as burst ROM space. CPU instruction fetches (only) can be
performed using a maximum of 4-word or 8-word continuous burst access. 1 state or 2 states can
be selected in the case of burst access.
7.5.2

Basic Timing

The AST0 bit of ASTCR sets the number of access states in the initial cycle (full access) of the
burst ROM interface. Wait states can be inserted when the AST0 bit is set to 1. The burst cycle
can be set for 1 state or 2 sttes by setting the BRSTS1 bit of BCRH. Wait states cannot be inserted.
When area 0 is set as burst ROM space, area 0 is a 16-bit access space regardless of the ABW0 bit
of ABWCR.
When the BRSTS0 bit of BCRH is cleared to 0, 4-word max. burst access is performed. When the
BRSTS0 bit is set to 1, 8-word max. burst access is performed.
Figure 7.14 (a) and (b) shows the basic access timing for the burst ROM space.
Figure 7.14 (a) is an example when both the AST0 and BRSTS1 bits are set to 1.
Figure 7.14 (b) is an example when both the AST0 and BRSTS1 bits are set to 0.
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