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Specifications
Serial Host Interface (SHI) I
6 × T
C
to
4096 × T
C
The programmed serial clock cycle (T
should be chosen in order to achieve the desired SCL serial clock cycle (T
Table 3-21.
Table 3-21 SCL Serial Clock Cycle (T
Filters bypassed
Narrow filters enabled
Wide filters enabled
EXAMPLE:
For DSP clock frequency of 120 MHz (i.e. T
environment (F
= 100 kHz (i.e. T
SCL
= 10µs - 2.5×8.33ns - 223ns - 1000ns = 8756ns
T
2
I
CCP
Choosing HRS = 0 gives
HDM[7:0] = 8756ns / (2 × 8.33ns × 8) - 1 = 64.67
Thus the HDM[7:0] value should be programmed to $41 (=65).
The resulting T
will be:
2
I
CCP
T
= [T
2
I
CCP
= [8.33ns × 2 × (65 + 1) × (7 × (1 – 0) + 1)]
T
2
I
CCP
= [8.33ns × 2 × 66 × 8] = 8796.48ns
T
2
I
CCP
3-64
2
C Protocol Timing
(if HDM[7:0] = $02 and HRS = 1)
(if HDM[7:0] = $FF and HRS = 0)
), SCL rise time (T
2
I
CCP
T
2
+ 2.5
I
CCP
T
2
+ 2.5
I
CCP
T
2
+ 2.5
I
CCP
= 10µs), T
SCL
× 2 × (HDM[7:0] + 1) × (7 × (1 – HRS) + 1)]
C
DSP56367
), and the filters selected
R
) Generated as Master
SCL
×
T
T
+ 45ns +
R
C
×
T
T
+ 135ns +
R
C
×
T
T
+ 223ns +
R
C
= 8.33ns), operating in a standard mode I
C
= 1000ns), with wide filters enabled:
R
), as shown in
SCL
2
C
MOTOROLA
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