Sony MDS-JA20ES Service Manual page 68

• AU BOARD IC100 CXD8607N (A/D CONVERTER)
Pin No. Pin Name
1 INRP
2 INRM
3 REFI
4 AVDD
5 AVSS
6 APD
7 NU
8 NU
9 TEST1
10 LRCK1
11 BCK1
12 ADDT
13 V35A
14 VSS1
MCKI
15
16 DPD
17 VSS2
18 RES
19 MODE
20 SHIFT
21 XLATCH
22 256CK
23 V35D
24 VSS2
25 512FS
26 BCK2
27 DADT
28 LRCK2
29 VDD2
30 R1
31 AVDDR
32 R2
33 AVSSR
34 XVDD
35 XOUT
36 XIN
37 XVSS
38 AVSSL
39 L2
I/O
I
R-ch analog signal (–) input terminal
I
R-ch analog signal (+) input terminal
I
Reference voltage (+3.3V) input terminal (for A/D converter section)
— Power supply terminal (+5V) (for A/D converter section, analog system)
—
Ground terminal (for A/D converter section, analog system)
I
Power down detection input of the A/D converter section (for analog section) "L": power down
—
Not used (open)
— Not used (open)
I
Input terminal for the test (fixed at "L")
L/R sampling clock signal (44.1 kHz) input from the CXD2654R (IC121) (for A/D converter
I
section)
I
Bit clock signal (2.8224 MHz) input from the CXD2654R (IC121) (for A/D converter section)
O
Recording data output to the CXD2654R (IC121)
—
Power supply terminal (+3.3V) (for analog system)
—
Ground terminal (for A/D converter section, digital system)
I
Master clock (256Fs=11.2896 MHz) input of the A/D converter section
Reset signal input from the system controller (IC800) Reset signal is used as a detection signal
I
of power down to A/D converter section (digital section) "L": reset (power down)
—
Ground terminal (for D/A converter section, digital system)
Reset signal input terminal Reset signal is used as a initialize signal to D/A converter section
I
"L": reset (initialize) Not used D/A converter section in this set
I
Writing data input terminal Not used (fixed at "L")
I
Serial clock signal input terminal Not used (fixed at "L")
I
Serial data latch pulse signal input terminal Not used (fixed at "L")
O
256Fs (11.2896 MHz) clock signal output terminal Not used (open)
—
Power supply terminal (+3.3V) (for digital system) Not used (open)
—
Ground terminal (for D/A converter section, digital system)
O
512Fs (22.5792 MHz) clock signal output terminal Not used (pull down)
Bit clock signal (2.8224 MHz) input terminal (for D/A converter section)
I
Not used (fixed at "L")
I
Playback data input terminal Not used (fixed at "L")
L/R sampling clock signal (44.1 kHz) input terminal (for D/A converter section)
I
Not used (fixed at "L")
Power supply terminal (+5V) (for D/A converter section, digital system)
—
Not used (fixed at "L")
O
R-ch PLM signal 1 output terminal Not used (open)
Power supply terminal (+5V) (for R-ch side D/A converter section, analog system)
—
Not used (fixed at "L")
O
R-ch PLM signal 2 output terminal Not used (open)
—
Ground terminal (for R-ch side D/A converter section, analog system)
— Power supply terminal (+5V) (for X'tal system) Not used (open)
O
System clock output terminal (22 MHz) Not used (open)
I
System clock input terminal (22 MHz) Not used (fixed at "L")
—
Ground terminal (for X'tal system)
—
Ground terminal (for L-ch side D/A converter section, analog system)
O
L-ch PLM signal 2 output terminal Not used (open)
Function
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