Diagrams; Block Diagram - Md Servo Section - Sony MDS-JA20ES Service Manual

Minidisc deck
Hide thumbs Also See for MDS-JA20ES:
Table of Contents

Advertisement

6-1. BLOCK DIAGRAM – MD SERVO Section –
HR901
OVER WRITE HEAD
I
I
1
J
J
2
F
B
C
B
I
J
D
A
A
A
4
B
5
E
C
AMP
6
DETECTOR
D
7
C
D
E
E
8
F
F
AMP
9
LASER DIODE
AUTOMATIC
APC
ILCC
POWER
LD/PD
11
CONTROL
AMP
Q162, 163
PD
LD
LASER ON
PD
PD
SWITCH
10
Q101
OPTICAL PICK-UP
(KMS-260A/J1N)
FOCUS/TRACKING COIL DRIVE,
SPINDLE/SLED MOTOR DRIVE
IC152
PSB
16
6
OUT4F
IN4R
3
M101
M
(SPINDLE)
8
OUT4R
IN4F
4
27
OUT2F
IN2F
29
M102
M
(SLED)
25
OUT2R
IN2R
30
2-AXIS
DEVICE
FCS+
21
OUT1F
IN1F
19
23
OUT1R
IN1R
18
FCS–
TRK+
12
OUT3F
IN3F
14
TRK–
10
OUT3R
IN3R
15
MOD
HF MODULE
05
SECTION 6

DIAGRAMS

OVER WRITE
HEAD DRIVE
IC181, Q181, 182
SCTX
RF AMP,
FOCUS/TRACKING ERROR AMP
IC101
48 47
RFO
AGCI
RF
RF AGC
RF AMP
46
40
38
& EQ
EQ
B.P.F.
AUX
33
WBL
3T
TEMP
PEAK
37
PEAK &
BOTM
BOTTOM
36
WBL
ADFM
ADIN
ADFG
AT
29
30
32
B.P.F.
AMP
I-V
ABCD
ABCD
35
AMP
FE
FOCUS
34
ERROR AMP
TE
26
I-V
TRACKING
SE
ERROR AMP
28
COMMAND
SERIAL/
PARALLEL
V-I
CONVERTER,
CONVERTER
DECODER
12
20
16
17
18
SPFD
SPRD
65
75
74
13
67
66
63
RECP
APCREF
AUTOMATIC
83
POWER
CONTROL
SFDR
ANALOG MUX
92
SRDR
91
A/D CONVERTER
DIGITAL
SERVO
SIGNAL
FROM CPU
PROCESS
FFDR
88
INTERFACE
FRDR
89
AUTO
SEQUENCER
TFDR
86
DIGITAL SERVO
TRDR
85
SIGNAL PROCESSOR
IC121 (2/2)
– 35 –
15
TX
EFMO
100
FILI
60
PCO
59
PLL
CLTV
62
FILO
61
ASYO
53
ASYI
54
COMPA-
RFI
RATOR
57
SUBCODE
ADIP
PROCESSOR
78
DEMODULATOR/
DECODER
CPU
F0CNT
SPINDLE
INTERFACE
79
SERVO
94 93
10
12
11
14
9 8
18
5 20 55 32
56
LDON
53
DIG-RST
59
WR-PWR
69
MOD
78
79
64
5
6
IN1
IN2
LOADING
MOTOR DRIVE
IC400
OUT1 OUT2
2
10
M
M10
(LOADING)
XLRF
XLAT
80
CKRF
SCLK
81
DTRF
SWDT
82
HF MODULE
SWITCH
IC103, Q102 – 104
IC121 (1/2)
ADDT
25
DATAI
22
DIGITAL SIGNAL PROCESSOR,
SAMPLING
XBCKI
EFM/ACIRC ENCODER/DECODER,
RATE
24
SHOCK PROOF MEMORY CONTROLLER,
CONVERTER
LRCKI
ATRAC ENCODER/DECODER
23
IC121 (1/2)
DIGITAL IN
DIN0
19
DIGITAL
DIN1
20
AUDIO
DOUT
DIGITAL OUT
INTERFACE
21
DADT
26
DADT, BCK, LRCK
28
27
29
512FS
OSCI
16
OSC
CLOCK
OSCO
IC123
GENERATOR
17
INTERNAL BUS
MONITOR
CONTROL
5 6 7
1 2 3 4
XOE
43
XWE
47
SWDT
XRAS
46
SCLK
XCAS
44
SWDT, SCLK
31 33 70
67 54 52 60
SCTX 65
SYSTEM CONTROLLER
IC800 (1/2)
LIMIT-IN
68
PLAY2
77
REFERENCE
B+
REC
76
VZ
4
VOLTAGE SWITCH
Q400, 401
PLAY1
75
80
LD-LOW
OPEN
74
REFLECT
57
PROTECT
58
– 36 –
MDS-JA20ES
ADDT
A
(Page 37)
B
(Page 38)
C
(Page 38)
D
(Page 37)
512FS
E
(Page 37)
D-RAM
IC124
16
XOE
3
XWE
4
XRAS
XCAS
17
F
(Page 37)
• SIGNAL PATH
: PLAY (ANALOG OUT)
: PLAY (DIGITAL OUT)
: REC (ANALOG IN)
: REC (DIGITAL IN)
S101
(LIMIT IN)
S13
(PLAY POSITION)
S12
(REC POSITION)
S11
(CHUCKING IN)
S10
(TRAY OPEN)
S102
(REFLECT/PROTECT DETECT)
HIGH REFELECT RATE/
WRITE PROTECT
LOW REFELECT RATE/
UN-PROTECT

Hide quick links:

Advertisement

Table of Contents
loading

Table of Contents