Sony CDX-V7800X Service Manual page 19
Fm/am multi media player
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Also See for CDX-V7800X:
- Operating instructions manual (58 pages) ,
- Installation/connections (4 pages) ,
- Service manual (56 pages)
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3 7 63 1515 0
Pin No.
146
147
RESERVED
148
149
150
151
152
153
RESERVED
154, 155
156
RESERVED
157
158
159
160
161
162
163, 164
DA-DATA1, 2
165
166
167
168
169
170
171
TE
L 13942296513
172
173
174
RESERVED
175
176
177
178
179
180
181
182
183
184
185
186 – 190
RESERVED
191
192
RESERVED
193
194
195
196
197
198
www
199
200
201
.
202 – 204
HADDR0 – 2
205
DTACKSEL
206
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Pin Name
I/O
VSS
—
Ground
I
Fixed at L in this set.
VDATA3
O
Video data bus 3 output
VDD
—
Power supply pin (+3.3 V)
VDATA4
O
Video data bus 4 output
VSS
—
Ground
VDATA5
O
Video data bus 5 output
I
Fixed at L in this set.
VDATA6, 7
O
Video data bus 6 and 7 output
I
Fixed at L in this set.
HSYNC
I/O
Horizontal sync input/output
VSYNC
I/O
Vertical sync input/output
NC
O
Not used. (Open)
VDD
—
Power supply pin (+3.3 V)
NC
O
Not used. (Open)
VSS
—
Ground
O
Serial audio samples relative to DA-BCK clock.
VDD2.5
—
Power supply pin (+2.5 V)
DA-LRCK
O
PCM left-right clock output
DA-BCK
O
PCM bit clock output
VDD2.5
—
Power supply pin (+2.5 V)
DA-XCK
O
Audio external frequency clock output
VSS
—
Ground
DAI-DATA
I
PCM input data, two channels.
DAI-LRCK
I
PCM input left-right clock
DAI-BCK
I
PCM input bit clock
I
Fixed at L in this set.
VDD
—
Power supply pin (+3.3 V)
A-VDD
—
Analog power supply pin (+3.3 V)
VCLK
I
Video clock input
SYSCLK
I
system clock input
A-VSS
—
Analog ground
CD-DATA
I
Serial CD data input
VDD
—
Power supply pin (+3.3 V)
CD-LRCK
I
Programmable polarity 16-bit word synchronization to the decoder (right channel HIGH).
VSS
—
Ground
CD-BCK
I
CD bit clock input
CD-C2PO
I
Asserted HIGH indicated a corrupted byte.
I
Fixed at L in this set.
NC
O
Not used. (Open)
I
Fixed at L in this set.
VDD
—
Power supply pin (+3.3 V)
NC
O
Not used. (Open)
VSS
—
Ground
VSS1
—
Ground
VDD2.5
—
Power supply pin (+2.5 V)
VSS1
—
Ground
VSS
—
Ground
x
ao
y
VSS1
—
Ground
HOST8SEL
I
Host select input
i
I
Host address bus 0 – 2 input
I
Data acknowledge select input
CS
I
Host chip select input
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8
Q Q
3
6 7
1 3
u163
.
2 9
9 4
2 8
Pin Description
1 5
0 5
8
2 9
9 4
m
co
9 9
2 8
9 9
19
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