Yamaha YSP-3000 Service Manual page 80

A B C
YSP-3000/YSP-30D/HTY-7030
DSP 2/2
1
2
3
4
5
3.3
1.3
0
3.3
3.3
3.3
3.3
0
6
1.3
1.7
0
1.3
0
1.7
0
0
0
1.7
1.3
0
3.3
0
0
1.3
0
WOOFER
7
0
1.3
3.3
0
1.3
0
1.3
3.3
0
1.3
3.3
0
0
1.3
1.3
8
0
9
# All voltages are measured with a 10MΩ/V DC electronic voltmeter.
# Components having special characteristics are marked s and must be replaced
with parts having specifications equal to those originally installed.
# Schematic diagram is subject to change without notice.
10
80
D E F
DAC
(SUBWOOFER)
3.3
1.7
0
0
1.7
1.7 3.3
SW
Page 79 C8
0
SUB
0 3.3
to DSP_CB1 WOOFER
3.3 4.9
0
0 2.5
CB3
5.0 2.5
0 3.3
3.3
0
3.3
3.3
0.1
1.3
0
0
0
0
0
DSP2 3.3
1.7
1.7
3.3
Sound equalization volume
0
0
1.3
2.9
IC13
2.9
2.9
2.9
2.9
2.9
3.3
0
1.3
2.9
2.9
2.9
2.9
No replacement part available.
2.9
2.9
2.9
1.3
0
3.3
2.9
2.9
2.9
3.1
0
3.1
3.3
0
1.3
G H I
DIGITAL IN
Page 81 J4
to INPUT_CB10
CB4
DAC
(WOOFER)
3.3
0
0
1.7 3.3
0
3.3
3.3 4.9
WOOFER L
2.5 0
0 2.5
5.0 2.5
CENTER
SURROUND
FRONT
DRAM FLASH ROM
3.3
0
2.9 2.9
3.3 0
0 0
2.9 2.9
0 3.3
2.9 2.9
0 0
0 3.3
0 2.9
2.9
2.9
0 2.9
2.9 3.3
0 2.9
3.3 0
0 2.9
2.9 2.9
0 2.9
2.9
2.9
0 2.9
0 3.3
2.9
2.9 2.9
3.3 2.9
3.3 0
3.3 3.3
3.1
3.3 2.9
3.3 3.1
0.1 2.9
1.7
3.3 2.9
3.3 3.3
0 2.9
3.3
0 2.9
0 0
1.7 2.9
0 0
1.6 2.9
0 0
3.2 2.9
0.1 1.7
3.2
0.1 1.6
3.2 0
3.2 3.2
3.2 3.3
3.2 3.2
0.1
3.3 0
J K
Page 81 J6 Page 85 L6
to INPUT_CB11 to POWER (1)_CB507
CB6 CB7
IC21
3.3
3.3
3.3
0 1.3
L M N
IC16: W9864G6GH-7
64 M x 4 banks SDRAM
CLK
CLOCK
BUFFER
CKE
CS
RAS
CAS
WE COLUMN DECODER COLUMN DECODER
CELL ARRAY CELL ARRAY
A10 BANK #0 BANK #1
MODE
A0
REGISTER
SENSE AMPLIFIER SENSE AMPLIFIER
A9
A11
BS0
BS1
DQ0
DATA CONTROL DQ
CIRCUIT BUFFER
DQ15
REFRESH COLUMN
COUNTER COUNTER UDQM
LDQM
COLUMN DECODER COLUMN DECODER
CELL ARRAY CELL ARRAY
BANK #2 BANK #3
SENSE AMPLIFIER SENSE AMPLIFIER
IC13: D60YA003BPYP225
Decoder
Digital Signal Processors
EMIF32 L2 Cache/
L1P Cache
Memory
Direct Mapped
4 Banks
McASP1 4K Bytes Total
64K Bytes
Total
McASP0
(4-Way)
C67x TM CPU
McBSP1
Instruction Fetch Control
Registers
McBSP0 Instruction Dispatch
Control
L2 Instruction Decode Logic
I2C1 Enhanced Memory
DMA Data Path A Data Path B Test
Controller
I2C0 DA610: A Register File B Register File
(16 channel) In-Circuit
192K Bytes
Emulation
Timer 1
DA601:
Interrupt
64K Bytes .L1t .S1t .M1t .D1 .D2 .M2t .S2t .L2t
Control
Timer 0
GP1
L1D Cache
2-Way Set
GP0 R2 ROM
Associative
512K
4K Bytes Total
Bytes
HPI16
Total
Clock Generator,
Oscillator and PLL Power-Down
x4 through x25 Multipliers Logic
/1 through /32 Dividers
IC14: TC7SH08FU
2-input AND gate
1
IN B 5 V CC
Page 83 A2
IN A 2
to AMP_CB501
GND 3 4 OUT Y
IC15, 17: WM8728
24-bit, 192 kHz stereo DAC
MODE LATI2S SCKDSD SDIDEM MUTEB CSBIWL ZERO
16 20 19 18 17 15 5
8 VOUTR
BCKIN 3
LRCIN 1
DIN 2 11 VOUTL
12 VMID
4 10 7 14 13 9 6
MCLK AVDD DVDD VREFP VREFN AGND DGND
IC18: MX29LV160CBTC-70G
16M-bit CMOS single voltage 3V only flash memory
WRITE
CE#
CONTROL
OE# PROGRAM/ERASE STATE
INPUT
WE#
HIGH VOLTAGE MACHINE
RESET# LOGIC
(WSM)
STATE
REGISTER
ADDRESS FLASH
ARRAY
LATCH
A0-A19 ARRAY
AND
SOURCE
HV
BUFFER
Y-PASS GATE
COMMAND
DATA
DECODER
SENSE PGM
AMPLIFIER DATA
HV
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q15/A-1
I/O BUFFER
A15 1 48 A16
A14 2 47 BYTE#
A13 3 46 GND
A12 4 45 Q15/A-1
A11 5 44 Q7
A10 6 43 Q14
A9 7 42 Q6
A8 8 41 Q13
A19 9 40 Q5
NC 10 39 Q12
WE# 11 38 Q4
RESET# 12 MX29LV160C T/B 37 VCC
NC 13 36 Q11
NC 14 35 Q3
RY/BY# 15 34 Q10
A18 16 33 Q2
A17 17 32 Q9
A7 18 31 Q1
A6 19 30 Q8
A5 20 29 Q0
A4 21 28 OE#
A3 22 27 GND
A2 23 26 CE#
A1 24 25 A0