Pci Sparse I/O Space Read/Write Encodings - Samsung AlphaPC 164UX Technical Reference Manual

PCI Sparse I/O Space
Table 1–8 contains the PCI sparse I/O space read/write encodings.
Table 1–8 PCI Sparse I/O Space Read/Write Encodings
Size
addr_h<4:3>
Byte 00
3
Word 01
Tribyte 10
Longword 11
Quadword 11
1
Byte enable set to 0 indicates that byte lane carries meaningful data
2
.
A<7> = addr_h<7>
3
Missing entries (for example, word size with 21164 address = 11) enjoy UNPREDICTABLE results.
System Address Space
A–24
Byte Offset 21164
addr_h Instruction
<6:5> Allowed
00
01
10 LDL,STL
11
00
01 LDL,STL
10
00
01 LDL,STL
00 LDL,STL
11 LDQ,STQ
PCI Byte
1
ad<2:0> Enable
2
A<7> ,00 1110
A<7>,00 1101
A<7>,00 1011
A<7>,00 0111
A<7>,00 1100
A<7>,00 1001
A<7>,00 0011
A<7>,00 1000
A<7>,00 0001
A<7>,00 0000
000 0000
.
Data-In Register
Byte Lanes
63.....32 31.......0
OOOX
OOXO
OXOO
XOOO
OOXX
OXXO
XXOO
OXXX
XXXO
XXXX
XXXX XXXX