Table of Contents
Advertisement
PCI Sparse Memory Space
A.7.1 Hardware Extension Register (HAE_MEM)
In sparse space, addr_h<7:3> are used to encode byte enable bits, size bits and the
low-order PCI address, ad<2:0>. This means that there are now five fewer address
bits available to generate the PCI physical address.
The system provides three sparse-space PCI memory regions and allows all three
sparse-space regions to be relocated by way of bits in the HAE_MEM register. This
provides software with great flexibility.
A.7.2 Memory Access Rules and Operation
The Alpha instruction set can express only aligned longword and quadword data ref-
erences. The PCI bus requires the ability to express byte, word, tribyte, longword
(double word), and quadword references. Intel processors are capable of generating
unaligned references, so the 21174 should be able to emulate the resulting PCI trans-
actions to ensure compatibility with PCI devices designed for Intel systems.
The size of the data transfer (byte, word, tribyte, longword, or quadword) and the
byte enables are encoded in the 21164 address. The 21164 signals addr_h<6:3> are
used for this purpose, leaving the remaining addr_h<31:7> signals to generate a PCI
longword address <26:3>
sparse 32-bit address space that maps to only 704MB of address space on the PCI.
The rules for accessing sparse space are as follows:
•
Sparse space supports all the byte encodings that may be generated in an Intel
system to ensure compatibility with PCI devices/drivers. The results of some
references are not explicitly defined. These are the missing entries in Table 1–6
(that is, word size with address<6:5> = 11). The hardware will complete the ref-
erence, but the reference is not required to produce any particular result, nor will
the system report an error.
•
Software must use longword load or store instructions (LDVSTL) to perform a
reference of longword length or less on the PCI bus. The bytes to be transferred
must be positioned within the longword in the correct byte lanes as indicated by
the PCI byte enable bits. The hardware does not shift bytes within the longword.
Quadword load and store instructions must be used only to perform quadword
transfers. Use of STQ/LDQ instructions for any other references will produce
UNPREDICTABLE results.
1 Quadword encoding is provided by way of 21164 address bits <6:3>. In this case, 21164
address bit <7> is treated as zero by the hardware.
System Address Space
A–18
1
. This loss of address bits has resulted in a 21164 22GB
Advertisement
Table of Contents
