Timing Of Host Interface (Multi Word Dma) - Toshiba R6472 - DVD±RW Drive - IDE Specifications

6.2.3. Timing of Host Interface (Multi word DMA)

Figure 10 shows the timings of the host interface Multi word DMA.
DMARQ
DMACK-*1
DIOR-/DIOW-*1
Read
DD0-15
Write
DD0-15
*1: In all timing diagrams, the low line indicator is negated and the upper line indicators asserted.
Multi word DMA
timing parameters min (ns) max (ns)
t0 Cycle time
tD DIOR-/DIOW- 16 bit
tE DIOR- data access
tF DIOR-data hold
tZ DMACK-to tristate
tG DIOR/DIOW-data setup
tH DIOW-data hold
tl DMACK to DIOR-/DIOW- setup
tJ DIOR-/DIOW- to DMACK hold
tKr DIOR- negated pulse width
tKw DIOW- negated pulse width
tLr DIOR- to DMARQ delay
tLw DIOW- to DMARQ delay
Figure 10 Timings of Host Interface (Multi Word DMA Mode 2)
t0
tD
tl
tE
tG
tF
tG tH
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tL
tK
Min time (ns)
120
70
5
20
10
0
5
25
25
TS-L532A (SD-R6472) Rev.1.1
tJ
tZ
Max time (ns)
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25
35
35