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Clock
Status
Instruction
5-clock Instrruction
Status:
System clock
CPU clock
Status
Instruction
5-clock Instrruction
Status:
Clock
Status
Instruction
PSET
Status:
S1C6200/6200A CORE CPU MANUAL
12-clock Instrruction
Interrupt
Interrupt processing:
Fetch
Execute
Note:
a) During instruction execution
HALT
Fetch
Execute
Note:
b) At HALT mode
CALL
Interrupt
Interrupt processing:
Fetch
Execute
Note:
c) During "PSET" instruction execution
Fig. A2.2.1 Timing chart of S1C6200A interrupt
APPENDIX A. S1C6200A (ADVANCED S1C6200) CORE CPU
INT1 (*1)
12-clock instruction
... 12.5 to 24.5 clock cycles
7-clock instruction
... 12.5 to 19.5 clock cycles
5-clock instruction
... 12.5 to 17.5 clock cycles
INT1 and INT2 are dummy instructions
(*1)
(*2)
Branches to the top of the interrupt service routine
INT1 (*1)
Interrupt
Interrupt processing: 14 to 15 clock cycles
(*1)
INT1 and INT2 are dummy instructions
(*2)
Branches to the top of the interrupt service routine
INT1 (*1)
INT2 (*1)
PSET + CALL
... 12.5 to 24.5 clock cycles
PSET + JP
... 12.5 to 22.5 clock cycles
INT1 and INT2 are dummy instructions
(*1)
(*2)
Branches to the top of the interrupt service routine
EPSON
INT2 (*1)
JP (*2)
INT2 (*1)
JP (*2)
JP (*2)
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