Ma intenance
Table 5-1.
Meanings of Self-test LED Indicator Patterns
LED
PATTERN
BEING DISPLAYED
TEST FAILURE SIGNIFIED
BY LED PATTERN
7
6
5
4
3
2
1
0
(WHICH TEST FAILED)
*
*
None
*
*
*
Basic Instr uction Set Test
*
*
*
ROM Test
*
*
*
SDLC Test
*
*
*
*
SDLC Test with DMA
*
*
*
BISYNC Test
*
*
*
*
BISYNC Test with DMA
0
0
0
0
*
*
*
RAM Test
*
*
*
*
RAM Test Par ity
Er
ror
*
*
*
*
Timer Interrupt Test
*
*
*
*
*
BISYNC and SDLC Tests w/DMA
Legend:
* =
LED 1 ighted
0
=
When 1 ighted, the coded pattern signifies which
chip (bit) has failed
(see table 5-2)
5-8