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Section VI
OR
NANO
NOR
XOR
BUF-
FER
INVERT-
ER
1-A-5-1
6-22
Model 7475A
INDICATOR SYMBOLS !Continued)
~~~~
.......
~~~~~~~..-~~~~~~~~--1
A
B
C
L
L
L
H
H
H
L
H
H
H
L
H
A
B
C
L
L
H
H
H
L
L
H
H
H
L
H
A
B
C
L
L
H
H
H
L
L
H
L
H
L
L
A B C
L
L
L
H H L
L
H
H
H
L
H
-m-
1
T
D
J-K
J-K (gated)
J-K !master
slave)
FF
T
s
FF
a
J
K
R
s
Toggles with
every clock
pulse
Data output
follows data
input. Input
is gated by C.
J
K
a
a
L L
N/C N/C
L H
L
H
H L
H
L
H H
toggles
J
and K inputs
are gated by
G.
This output is
dependent upon
negative going
edge of the signal.
S
Set input - when active causes the flip-flop to set (Asynchronous)
R
Reset input - when active causes the flip-flop to reset (Asynchronous)
N/C
No Change
Figure 6-23. ANSI Y32.14 Logic Symbols (Sheet 3 of6)
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