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1MRK 506 377-UEN Rev. L
TRM_40.CH1(I) I_CATENARY
TRM_40.CH2(I)
TRM_40.CH3(I) I_AT_NEUTRAL
TRM_40.CH7(U) U_CATENARY
TRM_40.CH8(U) U_FEEDER
CURRENTS_G1AI2P
VOLTAGES_G2AI2P
CURRENTS_G1AI2P
CURRENTS_G1AI2P
VOLTAGES_G2AI2P
CURRENTS_G1AI2P
VOLTAGES_G2AI2P
IEC18000068 V1 EN-US
Figure 35:
Verifying the case SystemType = 2Phase
1.
Apply the voltage and current as shown in Table 30:
Table 30:
Signal
UL
IECEQUATION15084 V1 EN-US
UL
IECEQUATION15085 V1 EN-US
IECEQUATION15086 V1 EN-US
IECEQUATION15087 V1 EN-US
2.
Wait for a few seconds and apply voltage and current according to Table
which fault loop is to be verified.
Railway application RER670
Commissioning manual
SMAI1
BLOCK
G1AI2P
GRP1L1
G1AI1
GRP1L2
G1AI2
G1AI3
GRP1L1L2
I_FEEDER
GRP1N
G1AI4
G1N
O:1IT:3II:1
SMAI2
BLOCK
G2AI2P
GRP2L1
G2AI1
GRP2L2
G2AI2
GRP2L1L2
G2AI3
G2AI4
GRP2N
G2N
O:1IT:3II:2
PRE PROCESSING
BACK UP OVER CURRENT PROTECTION
I_AT_N>
EF2PTOC
I2P*
TRIP
U2P*
TRSTP1
I2PDIR*
TRSTP2
BLOCK
TRDIRFW
BLKTR
START
I_AT_N>_START
BLKST1
STSTP1
BLKST2
STSTP2
STFW
STRV
ST2NDHRM
I_CATENARY>
D2PTOC
I2P*
TRIP
U2P*
TRSTP1
BLOCK
TRSTP2
BLKST1
START
I_CATENARY>_START
BLKTR1
STSTP1
BLKST2
STSTP2
BLKTR2
ST2NDHRM
DIR1
DIR2
UDIRLOW
CURRENT
I_CATENARY>_CURRENT
VOLTAGE
UIANGLE
I_FEEDER>
D2PTOC
I2P*
TRIP
U2P*
TRSTP1
BLOCK
TRSTP2
BLKST1
START
I_FEEDER>_START
BLKTR1
STSTP1
BLKST2
STSTP2
BLKTR2
ST2NDHRM
DIR1
DIR2
UDIRLOW
CURRENT
I_FEEDER>_CURRENT
VOLTAGE
UIANGLE
ACT configuration in PCM600 for ATCatenary type
Pre-fault voltages and current
Magnitude (Volts)
1
2
IL
1
IL
2
© 2017 - 2022 Hitachi Energy. All rights reserved
ZRCPDIS
CURRENTS_G1AI2P
I2P*
I_CATENARY_G1AI1
U2P*
I_FEEDER_G2AI2
BLOCK
VTSZ
I_AT_NEUTRAL_G1N
BLKTR
BLKZ1
BLKZ2
BLKZ3
BLKZ4
BLKZ5
VOLTAGES_G2AI2P
EXTRELZ1
U_CATENARY_G2AI1
EXTRELZ2
U_FEEDER_G2AI2
EXTRELZ3
EXTRELZ4
EXTRELZ5
DISTANCE PROTECTION
RWRFLO PHASE TRIGGERING LOGIC
I_CATENARY>_CURRENT
INPUT
I_FEEDER>_CURRENT
REF
I_AT_N>_START
I_CATENARY>_START
OR
I_REALCOMP_INHIGH
INPUT1
OUT
INPUT2
NOUT
I_REALCOMP_INEQUAL
INV_I_AT_N>_START
INPUT3
INPUT4
INPUT5
INPUT6
I_FEEDER>_START
OR
I_REALCOMP_INLOW
INPUT1
OUT
I_REALCOMP_INEQUAL
INPUT2
NOUT
INV_I_AT_N>_START
INPUT3
INPUT4
INPUT5
INPUT6
55
55
0
0
Testing functionality by secondary injection
TRIP
ZRCPDIS_TR
TRZ1
TRZ2
TRZ3
TRZ4
TRZ5
A1RADR
START
I_CATENARY_G1AI1
^GRPINPUT1
STZ1
I_FEEDER_G2AI2
^GRPINPUT2
STZ2
^GRPINPUT3
I_AT_NEUTRAL_G1N
STZ3
U_CATENARY_G2AI1
^GRPINPUT4
STZ4
^GRPINPUT5
U_FEEDER_G2AI2
STZ5
^GRPINPUT6
STNDZ1
^GRPINPUT7
STNDZ2
^GRPINPUT8
STNDZ3
^GRPINPUT9
STNDZ4
^GRPINPUT10
STNDZ5
STFW
ANALOG
STRV
DISTURBANCE
ZMAG
RECORDER
RMAG
XMAG
REALCOMP
INEQUAL
I_REALCOMP_INEQUAL
INHIGH
I_REALCOMP_INHIGH
INLOW
I_REALCOMP_INLOW
INV
INPUT
OUT
INV_I_AT_N>_START
RWRFLO
AND
PHSELL1*
CALCMADE
INPUT1
OUT
PHSELL2*
INPUT2
NOUT
CALCDIST*
FLT_DIST
INPUT3
INPUT4
FLT_LOOP
AND
INPUT1
OUT
INPUT2
NOUT
INPUT3
INPUT4
SECTL1L2
ZRCPDIS_TR
FLTRL1L2
FLTXL1L2
IEC15000393-2-en.vsdx
GUID-3E43344B-B8FB-4E46-9AB8-410D45155131 v2
Angle (Degrees)
31
depending on
Section 10
FLINVAL
FLT_X
FLT_R
DISTL1E
SECTL1E
FLTRL1E
FLTXL1E
DISTL2E
SECTL2E
FLTRL2E
FLTXL2E
DISTL1L2
0
180
0
180
147
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