HP 8340B Manual page 156

PLL2
Feedback
Loops
There are two feedback
paths
in
the PLL2 Loop (refer to Figure C-1):
Analog Feedback. The VCO output
is divided
by 500 (divided by
five twice and then divided
by 20)
and fed directly
to
the dischminator. Using the discriminator as the
feedback element produces the
equivalent of an extremely linear
VCO.
Phase-Locking Feedback Loop. The phase-locking feedback
loop
compares the output of the VCO
with
a
fixed
reference
signal,
even though the VCO frequency may be sweeping. The A42 PLL2
divider
converts the VCO frequency to
a
fixed
500 kHz
signal that retains the original VCO
signal's phase/
frequency error. The
A41 PLL2 phase detector compares
this signal to
a
500 kHz reference
signal,
and the
phase/frequency error
is
sampled and fed the the
A43 PLL2
discriminator.
The
discriminator
sums the error voltage with other tuning signals and tunes the A40 PLL2 VCO.
The following
is
a
general description of the PLL2
assemblies:
A40
PLL2 VCO
This voltage controlled oscillator
is
tuned by
a
summing amplifier on the
A43 PLL2 discriminator. The
VCO produces
a
75 to 150 MHz signal
that
is
divided to provide signals
of three different
resolutions.
As explained above, these outputs are required for operation at different YIG oscillator (YO)
sweep
widths, or for CW/Manual operation.
To
produce the different resolution signals, the 75 to 150 MHz VCO signal
is
divided by
5, 25,
or 500.
Signals that
are
divided by 25 or 500 are converted by PLL3 and
PLL1 for use by
the
YO
loop.
The A40 PLL2 VCO
has an analog
feedback loop output that goes to the
A43 PLL2 discriminator, and
a
phase-lock feedback loop output
that
goes to the A42 PLL2
Divider.
The PLL2 VCO
is
a
varactor-tuned transistor oscillator with
a
tuning range of 75 to 150
MHz. The
phase-lock loop allows
it to be programmed
in 5
kHz
steps
between
100 and 150
MHz.
The sweep
width can
be
as wide as 25
MHz
(PLL2
VCO sweeps
down
in
frequency) and as narrow as
500 kHz.
The output of the
VCO
is
divided by several digital frequency dividers and
are
sent to the destinations
shown
in Table C-2:
Table C-2.
20-30
Loop Frequency Range
us
Divider Configuration.
Output Of
PLL2 VCO
Divided by 5
Divided by
25
Divided by 500
Frequency Range
15
to
30 MHz
3
to
6
MHz
150 to 300
kHz
Destination
Used as
a
20-30 output
Sent to PLL3 Upconverter
Sent to PLL3 Upconverter
20-30
Loops Overall Theory of Operation
HP
8340B/41B