P5 (Pmc 33 To 64 I/O); P6 (Sata0) - GE CPCI3UX606 Hardware Reference Manual

10 CPCI3UX606

1.4.5 P5 (PMC 33 to 64 I/O)

NOTE
Availability of signals at this connector depends on the build option selected on the IMP3A.
PMC I/Os 47 to 64 are also not available if the IMP3A is System Controller.
Table 1-9 P5 Pin Assignments
Pin Signal Pin Signal
1 J14-33 2 J14-34
3 J14-35 4 J14-36
5 J14-37 6 J14-38
7 J14-39 8 J14-40
9 J14-41 10 J14-42
11 J14-43 12 J14-44
13 J14-45 14 J14-46
15 J14-47 16 J14-48
17 J14-49 18 J14-50
19 J14-51 20 J14-52
21 J14-53 22 J14-54
23 J14-55 24 J14-56
25 J14-57 26 J14-58
27 J14-59 28 J14-60
29 J14-61 30 J14-62
31 J14-63 32 J14-64
33 GND 34 GND
35 GND 36 GND

1.4.6 P6 (SATA0)

NOTE
Availability of signals at this connector depends on the build option selected on the IMP3A.
Use a right‐angled SATA cable to remain within the allowable height limit.
Table 1-10 P6 Pin Assignments
Pin Signal
1 GND
2 SATA0_TX+
3 SATA0_TX-
4 GND
5 SATA0_RX-
6 SATA0_RX+
7 GND
Publication No. CPCI3UX606-HRM/1