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4.
The setup sequence and operation of internal function blocks will start after setting Delay time
from the output level of Reference Clock Oscillator is over a certain level.
5.
Signal Detections (RSSI & Noise Detection) with operating cycle (Initial value: 1.35 ms) set by
register will start after the internal setup (about 0.22 ms) is finished.
6.
Start timing of the demodulation output (from DATA_IO pin) is varied with Bit Rate Filter
setting, data rate or other register settings. Preamble Detection output starts after the
demodulation output is obtained.
Voltage Supply
ENB
RESET
Control Command
（SPI）
Internal Regulator
(voltage)
Starting the system clock
input to logic circuit
Level of
Reference Clock
Internal Counter
Signal Detections
(RSSI / Noise Detection)
: at DET_TMONI1 / 2 pin
PLL_LD Signal
: at DET_TMONI1 / 2 pin
Demodulation Output
: at DATA_IO pin
Fig 6-29 Example of Boot Sequence Timing Chart (SPI Mode / RX)
* The example of timing chart may be omitted or simplified for explanatory purposes.
Notice:
-
To shorten the boot sequence of this IC, there is other way to be able to moving to Run without
going through Standby. In this method, firstly set ENB pin = "H", h'0A [D7] ENB = "1" and h'0A
[D6] ACT = "1", then set other registers. But in this way, if the internal setup and the register
setting are overlapped each other, unexpected operation may occur. To avoid above, make the SPI
speed too fast enough to communicate, or select the previous way as in Fig 6-29.
-
Check the relationship between supply voltage and reset, when to utilize the power on reset
during boot sequence. (See the notice in 6.3.1)
- Example of Boot Sequence 2: TX (in SPI Mode)
The following Fig 6-30 shows status transition from Battery Saving/Standby to TX-Run.
In this example, ENB pin and voltage supply are connected.
Register Setting: h‛0A[D7]ENB="1", h‛0A[D6]ACT="0"
Register Setting: h‛0A[D7]ENB="1", h‛0A[D6]ACT="1"
Register
Settings
105.5μs
Detection Setup
Detection Cycle Setting
0.338ms / 0.675ms / * 1.35ms / 2.70ms
High Impedance
Start of the demodulation output depends on Bit
Rate Filter setting or others.
47
Delay Time Setting
* 105.5μs / 211.1μs / 316.5μs / 527.5μs / 949.5μs
About 0.22ms
1.35ms
About
0.1ms
TC32306FTG
*: Initial Value
It indicates typical.
1.35ms
1.35ms
1.35ms
Demodulation Output
2015-10-01
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