Table of Contents
Advertisement
SUPPORT MATERIAL
ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005
The following documents are included in the appendix:
1.
Schematic diagram of MC145220EVK.
2.
Bill of materials.
3.
Parts layout diagram.
4.
Mechanical drawing of board.
5.
MC145220 data sheet.
6.
Typical signal plots.
PRODUCTION TEST
After assembly is complete, the following alignment and test is performed:
1.
The control program is started in '220 single loop mode.
2.
[L]! is selected to set PLL frequency to 733 MHz.
3.
Power is applied to the board. DIP switch section 1 is closed circuit with all others being open
circuit.
4.
After attaching computer cable, [I]! is selected.
5.
Trim resistor VR1 is adjusted to obtain an output frequency at J5 of 733 MHz
6.
Voltage at the control voltage test point (TP2) is measured. It must be > 0.5 V.
7.
[H]! is selected.
8.
Voltage at the control voltage test point (TP2) is measured. It must be < 4.4 V.
9.
[T]! is selected to toggle to PLL .
10. [L]! is selected to set PLL frequency to 790 MHz.
11. Voltage at the control voltage test point (TP9) is measured. It must be > 0.5 V.
12. [H]! is selected to set PLL frequency to 820 MHz.
13. Voltage at the control voltage test point (TP9) is measured. It must be < 4.4 V.
14. [G] is selected and the board type is changed to '220 dual loop mode.
15. [Q]!, then [I]!, is selected to initialize the dual mode output (J12) to 70 MHz. The frequency should
be 70 MHz
If in step 5 it isn't possible to obtain a signal on frequency, the adjustment screw in M1 may be turned for
further frequency adjustment range. If neither adjustment works, [P] should be selected and the correct
printer port address entered. [I]! is then selected to reload the data.
BOARD OPERATION
A computer is connected to the DB–25 connector J9. Data is output from the printer port. The printer card
is in slot 0 using the default address in the control program. Data is sent to the PLL device (U1) through
the DIP switch (S1), and 74HCT241 buffer (U2). D1, D2, D3, R7, R8, and R12 are in the data path be-
tween the 'HCT241 and PLL device. This limits the high level output voltage of the buffer. Voltage on PLL
device inputs must be no greater than 0.5 V above V+. A '220 PLL has three output lines which are
routed through a 74LS126 line driver (U3) back to the computer.
U2, the 74HCT241, provides isolation and logic translation for PLL input lines. Logic translation is need-
ed from the TTL levels on the printer port to the CMOS levels on the '220 inputs.
A 12 V power supply should be used to power the board at J8 (Augat 2SV–02 connector). The 2SV–02
will accept 18–24 AWG bare copper power leads. No tools are needed for connection. If power is proper-
ly connected, LED D4 will be lit.
MC145220EVK
8
Freescale Semiconductor, Inc.
50 Hz.
For More Information On This Product,
Go to: www.freescale.com
500 Hz.
MOTOROLA
Advertisement
Table of Contents
