Mitsubishi Electric MELSEC-A Series Manual page 112

2
REPLACEMENT OF MELSECNET (II) AND /B (PLC TO PLC NETWORK)
(4) Precautions for system where AnN/AnS/AnACPU are mixed.
Pay attention to the following when replacing the MELSECNET II system where AnN/AnA/AnSCPU
(excluding AnUS(H)CPU) are mixed, with the MELSECNET/10 system.
Refer to "Chapter 11 COMPOSITE SYSTEMS" in "Type MELSECNET/10 Network system (PLC to PLC
network) Reference Manual", for details.
(a) Control station of the MELSECNET/10 system
MELSECNET/10 system after transition requires one AnU/AnUS(H)/QnA/QnAS/QCPU as a control
station.
In addition, because AnN/AnA/AnSCPU (excluding AnUS(H)CPU) cannot be a sub-control station in
the transition to MELSECNET/10, the MELSECNET/10 system after transition requires two or more
AnU/AnUS(H)/QnA/QnAS/QCPU to use the control station shift function of MELSECNET/10.
(b) Device range where data link can be executed on the MELSECNET/10 system
Device range where data link can be executed on the MELSECNET/10 system is the device range of
AnN/AnS/AnACPU to be connected.
AnN/AnSCPU (excluding
AnUS(H)CPU)
AnACPU
*1 For A3NCPU. Depends on the number of I/O points that can be controlled by AnN/AnSCPU (excluding AnUS(H)CPU).
*2 For A3ACPU. Depends on the number of I/O points that can be controlled by AnACPU.
(c) When AnN/AnA/AnSCPU (excluding AnUS(H)CPU) are mixed in transition from
MELSECNET II composite mode to MELSECNET/10
Communicable B/W range is 0 to 3FF when AnN/AnSCPU (excluding AnUS(H)CPU) are mixed on
MELSECNET/10.
When the second half is set on the MELSECNET II composite mode, it is necessary to divide with
station inherent parameter for transferring data, but the station inherent parameter cannot be set on
AnN/AnSCPU (excluding AnUS(H)CPU).
AnACPU can communicate at the range of B/W0 to FFF, but station inherent parameter cannot be
set.
From here onwards, it may cause a communication error of the area divided by station inherent
parameter at the other station where transmission of B/W 400 or later cannot be made.
When replacing MELSECNET II composite mode with MELSECNET/10 where AnN/AnA/AnSCPU
(excluding AnUS(H)CPU) are mixed, replace AnN/AnA/AnSCPU (excluding AnUS(H)CPU) with a
CPU that is applicable to MELSECNET/10, such as QCPU.
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X/Y
*1
Maximum 0000 to 07FF
*2
Maximum 0000 to 07FF
B/Y
0000 to 03FF
0000 to 0FFF