NEC UPD98413 User Manual page 50

(b) Pointer processing of H1#1 and H2#1
The indication shown in Table 3-3 is interpreted depending on the NDF, SS bits, and pointer value extracted
from the H1#1 and H2#1 bytes.
Indication
1 norm_point
2 NDF_enable
3 AIS_ind
<2><3>
4
incr_ind
<2><3>
5 decr_ind
6 inv_point
<1> Whether the SS bits are checked when a pointer is interpreted can be specified by using the SSM bit of
the MDPTRR register, and the expected value to be verified can be set by using the SSR[1:0] bits of
the MDPTRR register. In the default mode, the SS bit are not checked.
<2> In the default mode, the condition of incr_ind indication is Three or more I-bits are inverted and three or
more D-bits are not inverted and decr_ind indication is Three or more I-bits are inverted and three or
more D-bits are not inverted, but this condition can be changed to mach of 8 bits or more of the 10 bits
I-bits and D-bits to either the increment and decrement indication. It can be changed by the FJM2 bits
of the MDPTRR register.
<3> In the default mode, this operation is executed under the condition that incr_ind, decr_ind, and
NDF_enable have not been received in the past three frames. If any of these indications has been
received, the indication is Inv_point. This condition can be invalidated by using the FJM2 bit of the
MDPTRR register.
<4> Conflict condition
• If the Frequency Justification operation is interpreted but the actual operation involves changing the
pointer value to a new value, the pointer value is changed after the Frequency Justification operation.
50
CHAPTER 3 FUNCTIONAL OUTLINE
Table 3-3. Pointer Interpretation
NDF SS Bits
<1>
Disable
Don't Care or coincidence
with expected value
<1>
Enable
Don't Care or coincidence
with expected value
1111 11
<1>
Disable
Don't care or coincidence
with expected value
<1>
Disable Don't care or coincidence
with expected value
Cases other than above or norm_point with current pointer value not equal to receive
pointer value.
PRELIMINARY
Pointer
Range of 0 to 782
Range of 0 to 782
All 1
Three or more I-bits are inverted and
three or more D-bits are not inverted.
Three or more I bits are not inverted
and three or more D bits are inverted.
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