Oh Extract Interfaces - NEC UPD98413 User Manual

4.4.2 OH Extract Interfaces

The OH extract interfaces are used to extract TOH and POH of a receive frame and output them to peripheral
devices.
1 Frame
19.44MHz
Row9
O)
ROHCK(
O)
RTOHFP(
O)
RPOHFP(
4
)
ROHAV(O
) Bit1 Bit3 Bit5 Bit7
ROHD[1](O
) Bit2 Bit4 Bit6 Bit8
ROHD[0](O
1st A1
Figure 4-22 shows the timing charts of the TOH and POH extract interface.
This interface outputs all TOH (POH) bytes of the receive frame. The µPD98413 outputs a 19.44-MHz clock that
is the receive clock extracted by the internal clock recovery divided by 36.
As TOH (POH) data, one byte is output to the 2-bit parallel data lines ROHD [1:0] in 4 clock cycles.
The µPD98413 outputs a pulse from RTOHFP (RPOHFP) to inform the external OH controller of the output start
position of TOH (POH) data. Output of the TOH data is started from the rising edge at which RTOHFP goes high.
After the output of the TOH data is complete, it begins the output of the POH data.
Output of the POH byte is started in sync with the rising edge at which RPOHFP goes high. In case of no
frequency justification, the output of POH data is 1 byte. In case of positive frequency justification, POH doesn't
sometimes exist. Therefore, in this case, makes ROHAV low to show by the dotted line of figure 4-22 and
doesn't output POH. In case of negative frequency justification, sometimes POH exists 2 bytes. Therefore, in
this case, ROHAV held high to show by the dotted line of figure 4-22 and output POH 2 bytes.
ROHAV is a signal by which the external OH controller is informed whether the µPD98413 is outputting valid
TOH and POH data on ROHD [1:0]. While the frame synchronization has been established and a valid TOH and
POH data is extracted, ROHAV is held high. If an alarm or fault such as LOS, LOF, OOF, and Line AIS is
detected in the reception line, the µPD98413 drives ROHAV low to indicate that the output data on ROHD [1:0] is
invalid.
CHAPTER 4 INTERFACES
Figure 4-22. Example of Timing Chart of POH Insert Interface
2 Frame
Row1
4
Bit1 Bit3 Bit5 Bit7 Bit1 Bit3 Bit5 Bit7
Bit2 Bit4 Bit6 Bit8 Bit2 Bit4 Bit6 Bit8
2nd A1 Z0
TOH
144 Clock (36x4)
PRELIMINARY
4 4
↓negative frequency justification
↑positive frequency justification
Bit1 Bit3 Bit5 Bit7 Bit1 Bit3 Bit5 Bit7
Bit2 Bit4 Bit6 Bit8 Bit2 Bit4 Bit6 Bit8
J1
POH
4 Clock
270 Clock
peripheral device
sampling
2 Frame
Row2
Bit1 Bit3 Bit5
Bit2 Bit4 Bit6
B1
IDLE
122 Clock
uPD98413
sampling
NEC confidential and Proprietary
143