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3.3.11
Latch-up
CMOS devices are subject to latch-up, an undesirable condition in which a parasitic PNPN junction
(thyristor) in the CMOS IC conducts. An abnormal current of several hundred mA can flow between
V
and GND, destroying the IC.
CC
Latch-up occurs when the voltage applied to the input or output pins exceeds the prescribed
absolute maximum rating value, causing a large current to flow in the device, or when the V
voltage exceeds (even momentarily) the absolute maximum rating value causing internal components
to break down. Latch-up results in a large, continuous current between V
overheating and burn-out. To avoid this, observe the following precautions.
(1) Ensure that the voltage level on the input/output pins is no higher than V
V
, taking into account the timing at power-on. (As the V
SS
device, please refer to the datasheet for the device in question.)
(2) Do not subject the device to abnormal noise.
(3) Fix the potential of any unused input pins to V
(4) Do not connect output pins directly to other output pins, or to V
Since ample margin against latch-up is provided, there is no problem if Min-CMOS devices are
used within their specifications. However, since the interface component may receive excessive
surges, it is recommended that protective circuits be added, as shown in Figure 3.5.
R
3.3.12
Electrical Discharge and Precautions against Noise
The Mini-MOS Series have ample margin for handling noise such as electrical discharge. Figure 3.6
show a circuit for ESD testing and Table 3.1 shows the results of ESD tests for various devices.
I/O
Figure 3.5 Example of Latch-up Prevention Methods
Input
or
Output
R
V
As
Figure 3.6 Test Circuit
CC
or V
.
CC
SS
R
I/O
EIAJ Method
MIL-STD Method : C = 100 pF
, GND
CC
104
[6] Handling Guide
and GND and can cause
CC
and no lower than
CC
and V
levels vary from device to
SS
or VSS.
CC
I/O
: C = 200 pF
R = 0 Ω
C = 1.5 kΩ
pin
CC
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