Block Diagram; Figure 13.2A Block Diagram Of Ie Bus - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

16-bit microcontrollers

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Table of Contents

13.2 Block Diagram

Uuit Address Register

Slave Address Register

Multiaddress Control Bit Set Register

Telegraph Length Set Register

Write Data Buffer (8-byte FIFO)

Master Address Read Register

Multiaddress Control Bit Read Register

Telegraph Length Set Register

Lock Read Register

Read Dta Buffer (8-byte FIFO)

Command Register

Status Register

Interrupt Request (Transmit, Receive)

Function of Control Circuitry

Chapter 13: IE Bus

Internal Clock

(12 MHz / 12.58 MHz)

1. Control the number of transmit/receive bytes

2. Control max. number of byte transmission

3. Detect arbitration

4. Determine acknowledgement

5. Generate interrupt

(6 MHz / 6.29 MHz)

MB90580 Series