11.4 Operations
Depending on the machine clock φ to be used, the communication prescaler register should be set as
follows. For details please refer to Chapter 12, UART.
.
machine clock
4 MHz
6 MHz
8 MHz
6 MHz
8 MHz
10 MHz
12 MHz
14 MHz
16 MHz
8 MHz
12 MHz
16 MHz
When using the machine clock and the div at a different setting other than those mentioned above, φ/div
should not exceed 4.25 MHz.
MB90580 Series
φ
div
DIV3
4
1
6
1
8
1
3
1
4
1
5
1
6
1
7
1
8
1
2
1
3
1
4
1
DIV2
DIV1
DIV0
1
0
0
0
1
0
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
0
0
1
0
0
0
1
1
0
1
0
1
1
0
0
Chapter 11: Communication Prescaler
11.4 Operations
φ
/div
1 MHz
2 MHz
4 MHz
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