Philips 32PFH5300 Service Manual page 34

EN 34 8. TPM15.1E LA
8.4 Diagram 10-4-13 DVB/T2/C/S2 Tuner
Block diagram
RFAGC
ADC_I
ADC_Q
Pinning information
2015-Jun-12
IC Data Sheets
B13, AVL6211LA (IC U104)
AVL 6211
Carrier
Phase
Recovery
Dual
Digital Front-end
10 - Bit
Down Converter
ADC
Symbol
PLL
Timing
Recovery
DiSEqC
Tuner
2.0
Control
Control
Interface
Interface
A A DC_AVDD 1
ADC_AVSS 2
ADC_IP 3
ADC_IN 4
ADC_AVSS 5
ADC_AVDD 6
ADC_QP 7
ADC_QN 8
PLL_AVDD 9
PLL_AVSS 10
VDDC 11
GND 12
VDDC 13
PLL_REFCLK_XI 14
PLL_REFCLK_XO 15
RFAGC 16
Figure 8-6 Internal block diagram and pin configuration
PL Frame
Processor
Equalizer
Two -wire
Bus
Controller
AVL6211LA
TOP VIEW
(Not to Scale)
back to
div.table
DVB FEC
Viterbi/RS
Decoder
TS Output
Interface
LDPC &
BCH FEC
Decoder
JTAG
48 VDDC
47 GND
46 MPEG_ERR
45 MPEG_SYNC
44 MPEG_VALID
43 VDDIO
42 GND
41 VDDC
40 MPEG_CLK
39 MPEG_DATA_0
38 MPEG_DATA_1
37 GND
36 VDDIO
35 VDDC
34 MPEG_DATA_2
33 MPEG_DATA_3
MPEG TS
Output
19600_304.eps