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Communications Processor Module (CPM) Ports
General-
Purpose
1-22
Table 1-3. Port A Signals (Continued)
Name
Peripheral Controller:
Dedicated Signal
I/O
Protocol
PA22
FCC1: TXD3
UTOPIA
PA21
FCC1: TXD4
UTOPIA
FCC1: TXD3
MII and HDLC nibble
PA20
FCC1: TXD5
UTOPIA
FCC1: TXD2
MII and HDLC nibble
PA19
FCC1: TXD6
UTOPIA
FCC1: TXD1
MII and HDLC nibble
Dedicated
I/O Data
Direction
Output
FCC1: UTOPIA Transmit Data Bit 3
TXD[0–7] is part of the ATM UTOPIA interface supported by
FCC1. The MSC8101 outputs ATM cell octets (UTOPIA
interface data) on TXD[0–7]. TXD7 is the most significant
bit. TXD0 is the least significant bit. When no ATM data is
available, idle cells are inserted. A cell is 53 bytes.
Output
FCC1: UTOPIA Transmit Data Bit 4
TXD[0–7] is part of the ATM UTOPIA interface supported by
FCC1. The MSC8101 outputs ATM cell octets (UTOPIA
interface data) on TXD[0–7]. TXD7 is the most significant
bit. TXD0 is the least significant bit. When no ATM data is
available, idle cells are inserted. A cell is 53 bytes.
Output
FCC1: MII and HDLC Nibble Transmit Data Bit 3
TXD[3–0] supports MII and HDLC nibble modes in FCC1.
TXD3 is the most significant bit. TXD0 is the least significant
bit.
Output
FCC1: UTOPIA Transmit Data Bit 5
TXD[0–7] is part of the ATM UTOPIA interface supported by
FCC1. The MSC8101 outputs ATM cell octets (UTOPIA
interface data) on TXD[0–7]. TXD7 is the most significant
bit. TXD0 is the least significant bit. When no ATM data is
available, idle cells are inserted. A cell is 53 bytes.
Output
FCC1: MII and HDLC Nibble Transmit Data Bit 2
TXD[3–0] is supported by MII and HDLC nibble modes in
FCC1. TXD3 is the most significant bit. TXD0 is the least
significant bit.
Output
FCC1: UTOPIA Transmit Data Bit 6
TXD[0–7] is part of the ATM UTOPIA interface supported by
FCC1. The MSC8101 outputs ATM cell octets (UTOPIA
interface data) on TXD[0–7]. TXD7 is the most significant
bit. TXD0 is the least significant bit. When no ATM data is
available, idle cells are inserted. A cell is 53 bytes.
Output
FCC1: MII and HDLC Nibble Transmit Data Bit 1
TXD[3–0] is supported by MII and HDLC transparent nibble
modes in FCC1. TXD3 is the most significant bit. TXD0 is
the least significant bit.
Description
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