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Layout Practices
4.4 Layout Practices
Each
power supply. Similarly, each
power supply pins drive distinct groups of logic on the chip. The
to ground using at least four 0.1 µF by-pass capacitors located as closely as possible to the four sides of
the package. The capacitor leads and associated printed circuit traces connecting to chip
GND
employing two inner layers as
All output pins on the MSC8101 have fast rise and fall times. Printed circuit board (PCB) trace
interconnection length should be minimized in order to minimize undershoot and reflections caused by
these fast output switching times. This recommendation particularly applies to the address and data
busses. Maximum PCB trace lengths of six inches are recommended. Capacitance calculations should
consider all device loads as well as parasitic capacitances due to the PCB traces. Attention to proper PCB
layout and bypassing becomes especially critical in systems with higher capacitive loads because these
loads create higher transient currents in the
signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the
PLL supply pins.
There are 2 pairs of PLL supply pins:
PLL. To ensure internal clock stability, filter the power to the
similar to the one in Figure 4-2.. To filter as much noise as possible, place the circuit as close as possible
to
the 10-µF capacitor, the 10-nH inductor, and finally the 10-Ω resistor to
short and direct.
GND
be bypassed to
the chip package. The user should also bypass
0.01-µF capacitor as closely as possible to the chip package
4-4
and
pin on the MSC8101 should be provided with a low-impedance path to the board's
V
V
CC
DD
GND
should be kept to less than half an inch per capacitor lead. A four-layer board is recommended,
V
and
. The 0.01-µF capacitor should be closest to
V
V
CCSYN
CCSYN1
and
should be provided with an extremely low impedance path to ground and should
GND
SYN
SYN1
and
V
V
CCSYN
CCSYN1
V
DD
10Ω
Figure 4-2. VCCSYN and VCCSYN1 Bypass
pin should be provided with a low-impedance path to ground. The
and
planes.
GND
CC
,
, and
V
V
GND
CC
DD
V
-
GND
and
V
CCSYN
SYN
, respectively, by a 0.01-µF capacitor located as close as possible to
and
GND
GND
SYN
10nH
10 µF
power supply should be bypassed
V
CC
V
CC
circuits. Pull up all unused inputs or
-
GND
. Each pair supplies one
CCSYN1
SYN1
and
inputs with a circuit
V
V
CCSYN
CCSYN1
and
, followed by
V
V
CCSYN
CCSYN1
. These traces should be kept
V
DD
to
and
V
V
SYN1
CCSYN
CCSYN1
V
CCSYN
0.01 µF
,
V
, and
DD
with a
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