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3.3 Timers
The V7768/V7769 provide four user-programmable timers (two 16-bit and two
32-bit) which are completely dedicated to user applications and are not required
for any standard system function. Each timer is clocked by independent
generators with selectable rates of 2 MHz, 1 MHz, 500 kHz and 250 kHz. Each
timer may be independently enabled and each is capable of generating a system
interrupt on timeout.
Events can be timed by either polling the timers or enabling the interrupt
capability of the timer. A status register allows for application software to
determine which timer is the cause of any interrupt.
3.3.1 Timer Control Status Register 1 (TCSR1)
The timers are controlled and monitored via the Timer Control Status Register 1
(TCSR1) located at offset 0x00 from the address in BAR2. The mapping of the bits
in this register are shown in Table 3-2.
Table 3-2 TCSR1 Bit Mapping
Field
Timer 1 Caused IRQ
Timer 1 Enable
Timer 1 IRQ Enable
Timer 1 Clock Select
Timer 2 Caused IRQ
Timer 2 Enable
Timer 2 IRQ Enable
Timer 2 Clock Select
Timer 3 Caused IRQ
Timer 3 Enable
Timer 3 IRQ Enable
Timer 3 Clock Select
Timer 4 Caused IRQ
Timer 4 Enable
Timer 4 IRQ Enable
Timer 4 Clock Select
Reserved
All of these bits default to "0" after system reset.
Each timer has an independently selectable clock source which is selected by the
bit pattern in the "Timer x Clock Select" field as shown in Table 3-3.
Table 3-3 Selectable Clock Source for Timers
Clock Ratio
2 MHz
1 MHz
500 kHz
250 kHz
Bits
Read or Write
TCSR1[0]
R/W
TCSR1[1]
R/W
TCSR1[2]
R/W
TCSR1[4..3]
R/W
TCSR1[8]
R/W
TCSR1[9]
R/W
TCSR1[10]
R/W
TCSR1[12..11]
R/W
TCSR1[16]
R/W
TCSR1[17]
R/W
TCSR1[18]
R/W
TCSR1[20..19]
R/W
TCSR1[24]
R/W
TCSR1[25]
R/W
TCSR1[26]
R/W
TCSR1[28..27]
R/W
All Other Bits
R/W
MSb
LSb
0
0
0
1
1
0
1
1
Embedded PC/RTOS Features 47
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