Address Generation Pipeline Interlocks; What Are The Address Generation Pipeline Interlocks - Motorola DSP56600 Manual

6.2 ADDRESS GENERATION PIPELINE
INTERLOCKS
There are sequences related to the Address Generation Unit that
cause the insertion of one, two or three pipeline interlock cycles.
These paragraphs describe what are these sequences and suggest
few ways to avoid them in the application.
6.2.1 What are the Address Generation Pipeline
Interlocks
There are two types of Address Generation pipeline interlock:
• Tcc Interlock is caused by a Transfer On-Condition (Tcc)
instruction that specified one of the address registers as its
destination. If the following instruction specifies the same
address registers as its source operand, than the execution of
this instruction will be delayed by one instruction cycle.
Example:
Tcc
move
• Address Generation Interlock is caused by a MOVE
instruction that uses one of the AGU registers R0–R7 for
address generation, while one of the three preceding
instructions used one of the register-set (Ri, Ni or Mi)
members as a destination register.
Example:
move
move
move
Up to three interlock cycles are added to the execution of the
instruction that caused the interlock, depending on the distance (in
instruction words) between this instruction and the preceding
instruction that used one of the register set members (Ri, Ni or Mi)
as a destination register. In the example above, the distance is 0,
thus three interlock cycles will be added. In the next example, only
one interlock cycle will be added to the execution of the first MPY
MOTOROLA Optimizing DSP56300/DSP56600 Applications
A1,B r0,r1 ;Tcc instruction. R1 is
;conditional destination
r1,x0 ;R1 is source operand
#addr,R0 ;R0 is destination
#offset,N0 ;N0 is destination
X:(r0)+,y1 ;Instruction uses R0

Address Generation Pipeline Interlocks

Pipeline Interlocks
6-7