Features - Panasonic MN103SFX1K Manual

1.3

Features

This LSI's features are described.
CPU (MN103S core)
Structure
Minimum instruction execu-
tion cycle
Number of basic instruc-
tions
Number of addressing
modes
Basic instruction length
Memory space
Internal memory
Internal ROM capacity
Sector size
Internal RAM capacity
Extended calculation function
Extended calculation in-
struction
Clock generator
External oscillation (crystal/
ceramic)
Clock multiplying circuit
(PLL)
Operation mode
CPU operation mode
Standby mode
Interrupt Controller
Internal interrupt
External interrupt
Reset function
Pin reset
Software reset
Power supply detection reset Detection level: 3.6 V to 4.3 V
Publication date: April 2018
LOAD/STORE architecture with 5-stage pipeline
13.9 ns (72 MHz)
(External oscillation frequency 8MHz, 9 multiplying)
46
6
1 byte
Linear address space of 4 GB (for instructions / data)
Large sector
Small sector
High-speed multiplication, High-speed division, trigonometric function, absolute value,
square root, LPF, 3-phase/2-phase conversion, PI calculation
Product-sum operation of n-th degree, Saturate calculation
4 to 16 MHz
4 to 12 multiplying
NORMAL mode
SLEEP mode, HALT mode, STOP mode
Watchdog timer overflow, System error
Timer, Serial, PWM, A/D conversion
A/D conversion error detection, Comparator detection
External interrupt pin input
Edge detection or Level detection can be selected
Control NRST pin from outside
Writing to register
MN103SFX1K/X2K/X3K/X5K/X6K/X7K
256 KB (Flash Memory)
32 KB (Total 224 KB)
8 KB (Total 32 KB)
12 KB
32-bit Single-chip Microcontroller
PubNo. 232X701-015E
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