Panasonic MN102F75K Manuals

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Panasonic MN102F75K User Manual

Panasonic MN102F75K User Manual (338 pages)

PanaX Series Microcomputer

Brand: Panasonic | Category: Computer Hardware | Size: 6.13 MB

Table of Contents

Table of Contents
4
About this Manual

17
- Using this Manual
  17
- Text Conventions
  17
- Register Conventions
  17
- Related Documents
  18
- Questions and Comments
  18
1 General Description

19
- MN102H Series Overview
  19
- MN102H Series Features
  19
- Conventional Vs. MN102H Series Code Assignments
  20
- Three-Stage Pipeline
  20
- MN102H Series Interrupt Servicing
  21
- MN102H Series Description
  22
- Internal Registers, Memory, and Special Function Registers
  24
- Address Space
  25
- Interrupt Controller Configuration
  26
- Interrupt Servicing Sequence
  26
- General Specifications
  27
- Block Diagram
  29
- Functional Block Diagram
  29
- Block Diagram Explanation
  30
- Pin Descriptions
  31
- MN102H85K Pin Description
  31
- MN102H85K Pin Configuration in Single-Chip Mode
  31
- MN102H75K Pin Description
  32
- MN102H75K Pin Configuration in Single-Chip Mode
  32
- Pin Functions
  33
- Power Supply Wiring
  35
- Osc1And OSC2 Connection Examples
  35
- Reset Pin Connection Example 1
  35
- OSDXI and OSDXO Connection Examples
  35
- Bus Interface
  36
  - Description
    36
- Memory Space in External Extension Mode
  36
- Bus Interface Control Registers
  37
- Wait Count Settings
  37
2 Interrupts

38
3 Low-Power Modes

73
4 Timers

78
5 Serial Interfaces

128
6 Analog-To-Digital Converter

144
- Description
  144
- Features
  144
- ADC Functions and Features
  144
- ADC Architecture
  144
- Block Diagram
  145
- A/D Conversion Timing
  145
- Selecting the ADC Clock Source
  145
- ADC Block Diagram
  145
- ADC Timing
  145
- Single Channel/Single Conversion Timing
  146
- Multiple Channel/Single Conversion Timing
  146
- Single Channel/Continuous Conversion Timing
  147
- Multiple Channel/Continuous Conversion Timing
  147
- ADC Setup Examples
  148
- Setting up Software-Controlled Single-Channel A/D Conversion
  148
- Single-Channel A/D Conversion
  148
- Setting up Hardware-Controlled Intermittent Three-Channel A/D Conversion
  149
- Timing of Software-Controlled Single-Channel A/D Conversion
  149
- Multiple-Channel A/D Conversion
  149
- ADC Control Registers
  151
- Timing of Hardware-Controlled Intermittent Three-Channel A/D Conversion
  151
- Caution about Analog-To-Digital Converter
  153
- Cautions on Analog-To-Digital Converter
  153
7 On-Screen Display

154
- Description
  154
- Features
  154
- OSD Functions and Features
  154
- Block Diagram
  155
- Power-Saving Considerations in the OSD Block
  156
- Power-Saving Control Bits for the OSD
  156
- OSDPOFF and OSDREGE Settings
  156
- OSD Operation
  157
  - OSD Clock
    157
- External Input Sync Signals
  157
- Multi-Layer Format
  157
  - Output Pin Setup
    158
- Microcontroller Interface
  158
  - Vram
    158
- Conditions for VRAM Writes
  159
- Standard and Extended Display Modes
  160
- Cursor Layer Display Modes
  160
- Cursor Tiles in Standard and Extended Modes
  160
- Graphics Layer Display Modes
  161
- Associated Tiles for Cursor Tile Code Registers
  161
- Graphic Tiles in Standard and Extended Modes
  161
- Display Setup Examples
  162
- Setting up the Graphics Layer
  162
- Example Graphics VRAM Settings
  162
- Graphics Display Example
  163
- Setting up the Text Layer
  164
- Example Text VRAM Settings
  164
- Text Display Example
  165
- Vram
  166
  - VRAM Operation
    166
- VRAM Bit Allocation in Internal RAM
  166
- VRAM Organization
  170
- VRAM Organization (When GEXTE = 0)
  170
- Graphics VRAM Organization for Two Modes
  171
- Cautions about the Number of Display Code Set to VRAM
  172
- Timing for OSD Data
  172
- Rom
  173
  - ROM Organization
    173
- Graphics ROM Organization in Different Color Modes
  174
- Graphics ROM Setup Example for a Single Line
  174
- Graphics ROM in the Four Color Modes (16W X 16H Tiles)
  175
- Graphics ROM in the Four Color Modes (16W X 18H Tiles)
  176
- Graphics ROM Organization in 16-Color Mode (16W X 16H Tiles)
  177
- Graphics ROM Organization in 8-Color Mode (16W X 16H Tiles)
  177
- Graphics ROM Organization in 4-Color Mode (16W X 16H Tiles)
  177
- Graphics ROM Organization in 2-Color Mode (16W X 16H Tiles)
  177
- Graphics ROM Organization in 16-Color Mode (16W X 18H Tiles)
  178
- Graphics ROM Organization in 8-Color Mode (16W X 18H Tiles)
  178
- Graphics ROM Organization in 4-Color Mode (16W X 18H Tiles)
  178
- Graphics ROM Organization in 2-Color Mode (16W X 18H Tiles)
  178
- Setting up the OSD
  179
- Setting up the OSD Display Colors
  179
- Color Palette Registers
  179
- RGB, YM, and YS Output Control Settings
  182
- OSD Signal Waveform
  183
- OSD Signal Output Switches
  184
  - Text Layer Functions
    185
- Character Outlining Example
  185
- Character Shadowing Example
  185
- Box Shadowing Example
  186
- Italicizing and Underlining Example
  187
  - Display Sizes
    188
- Graphic Tile Size Combinations
  188
- Character Size Combinations
  189
- Setting up the OSD Display Position
  190
- DMA and Interrupt Timing
  192
- DMA and Interrupt Timing for the OSD
  193
- Selecting the OSD Dot Clock
  194
- OSD Dot Clock Source Settings
  194
- OSD Dot Clock Division Settings
  194
- Controlling the Shuttering Effect
  195
- Controlling the Shuttered Area
  195
- Bit Settings for Controlling the Shuttered Area
  195
- Shuttered Area Setup Examples
  196
- Controlling Shutter Movement
  197
- Bit Settings for Controlling Shutter Movement
  197
- Shutter Movement Setup Examples
  198
- Controlling Shuttering Effects
  199
- Bit Settings for Controlling Shuttering Effects
  199
- Text-Layer Shuttering Setup Examples
  200
- Controlling Line Shuttering
  201
- Shutter Blanking Setup Examples
  201
- Line Shuttering Setup Example
  201
- Field Detection Circuit
  202
  - Block Diagram
    202
  - Description
    202
- Field Detection Circuit Block Diagram
  202
- Field Detection Timing
  202
- Considerations for Interlaced Displays
  203
- EOMON Output Criteria
  203
- OSD Registers
  204
- Cursor Vertical Size Settings
  206
- Graphics Vertical Size Settings
  207
- Text Vertical Size Settings
  208
8 IR Remote Signal Receiver

217
- Description
  217
- MN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company
  218
- Block Diagram
  218
- IR Remote Signal Receiver Block Diagram
  218
- IR Remote Signal Receiver Operation
  219
  - Operating Modes
    219
  - Noise Filter
    219
- IR Remote Signal Noise Filtering
  219
  - 8-Bit Data Reception
    220
- Reception of 8-Bit Data with no Leader
  220
- Reception of 8-Bit Data with Leader
  220
- Identifying the Data Format
  221
- Logic Level Conditions for Data Formats
  221
- Long and Short Data Identification
  221
- Conditions for Detecting Data Formats
  221
  - Generating Interrupts
    222
    
    Leader Detection
    222
    
    Trailer Detection
    222
- 8-Bit Data Reception Detection
  222
  - Pin Edge Detection
    222
- Leader Detection Conditions
  222
- Controlling the SLOW Mode
  223
- Differences between SLOW and NORMAL Modes
  223
- IR Remote Signal Receiver Control Registers
  224
- IR Remote Signal Receiver Registers
  224
- HEAMA and 5-/6-Bit Data Pulse Widths
  224
9 Closed-Caption Decoder

228
- Description
  228
- Block Diagram
  228
- Pins Used for CCD0 and CCD1
  228
- Closed-Caption Decoder Block Diagram
  228
- Functional Description
  229
- Analog-To-Digital Converter
  229
- Recommended ADC Configuration
  229
- External Connection with both CCD0 and CCD1 Unused
  229
- External Connection with Only CCD1 Unused
  229
  - Clamping Circuit
    230
- Caption Decoder Register Setting
  230
- Clamping Reference and Compare Levels
  230
  - Sync Separator Circuit
    231
- Current Level Control
  231
- Control Registers for Clamping Circuit
  231
  - HSYNC Separator
    233
- Control Registers for Sync Separator Circuit
  233
- HSYNC Securement and Interpolation
  233
  - VSYNC Separator
    234
- Field Detection Circuit
  234
  - Data Slicer
    234
- VSYNC Masking
  234
- Data Slice Level Calculation
  234
- Controller and Sampling Circuit
  235
- Control Registers for Data Slicer
  235
- Control Registers for Controller and Sampling Circuit
  235
- CRI Detection for Sampling Clock Generation
  236
  - Data Capture Control
    236
- Sampling Clock Timing Determination
  236
- Caption Data Capture Timing
  236
- Closed-Caption Decoder Registers
  237
- Closed-Caption Decoder Register
  237
- SLSF and SLHD Multiplexing
  239
- Backporch Position Setting
  245
- Sync Separator Level
  245
- BSP and PSP Multiplexing
  246
10 Pulse Width Modulator

250
- Description
  250
- Register Settings for Internal PWM Pullup
  250
- PWM Output Waveform
  250
- Block Diagram
  251
- PWM Data Registers
  251
- PWM Block Diagram
  251
I/O Ports

252
- Description
  252
- I/O Port Pins
  252
- I/O Port Circuit Diagrams
  253
- P00/RMIN/IRQ0 (Port 0)
  253
- P03/ADIN0 to P07/ADIN4 (Port 0)
  254
- P10/ADIN5/IRQ1, P11/ADIN6/IRQ2, and P12/ADIN7/IRQ3 (Port 1)
  255
- P13/ADIN8/WDOUT and P14/ADIN9/STOP (Port 1)
  256
- P15/ADIN10/PWM0 and P16/ADIN11/PWM1 (Port 1)
  257
- PWM2 (Port 1), P20/PWM3, P21/PWM4, P22/PWM5, and P23/PWM6 (Port 2)
  258
- P24/TM4IC/SBT1 (Port 2)
  259
- P27/TM0IO (Port 2)
  260
- P35/DAROUT/R, P36/DAGOUT/G, P37/DABOUT/B (Port 3), and P40/DAYMOUT/YM (Port 4)
  261
- P25/TM4IOB/SBI1/SBD1 and P26/TM4IOA/SBO1 (Port 2)
  262
- P55 and P56 (Port 5)
  263
- P57/SBT0 (Port 5)
  264
- P02/SCL1 (Port 0) and P61/SCL0 (Port 6)
  265
- P01/SDA1 (Port 1) and P60/SDA0 (Port 6)
  266
- P31/CVBS0 and P32/CVBS1 (Port 3)
  267
- P30/CLH and P33/CLL (Port 3)
  268
- P34/VREF (Port 3)
  269
- P41/TM1IO, P42/TM5IOA, and P43/TM5IOB/HI0 (Port 4)
  270
- P44/TM5IC/HI1 (Port 4)
  270
- P45/OSDXO and P46/OSDXI (Port 4)
  271
- P47/HSYNC (Port 4)
  272
- P50/SYSCLK (Port 5)
  273
- P51/YS (Port 5)
  274
- P52/IRQ4/VI0 (Port 5)
  275
- P53/RST (Port 5)
  276
- P54/IRQ5/VSYNC (Port 5)
  277
- I/O Port Control Registers
  278
12 ROM Correction

289
- Description
  289
- ROM Area Schematic Diagram
  289
- ROM Correction Flow
  289
- Block Diagram
  290
- Programming Considerations
  290
- ROM Correction Block Diagram
  290
- ROM Correction Control Registers
  291
- ROM Correction Address Match and Data Registers
  291
100 C Bus Controller

294
- Description
  294
- Example of I
  294
- Operating Modes for Devices on an I 2 C Bus
  295
- Connection of Two Microcontrollers to the I
  295
- C Bus Interface Operation
  296
- Block Diagram
  297
- Functional Description
  297
- Control Registers for Clamping Circuit
  297
- C Bus Controller Block Diagram
  297
- Setting up the I
  299
- Registers Settings for SDA0/SCL0 or SDA1/SCL1 Ports
  299
- Pin Control Circuit for the I
  299
- SDA and SCL Waveform Characteristics
  300
- SDA and SCL Waveforms
  300
- I 2 C Interface Setup Examples
  301
- Setting up a Transition from Master Transmitter to Master Receiver
  301
- Pre-Configuring
  301
- Setting up the First Interrupt
  301
- Setting up the Second Interrupt
  302
- Setting up the Third Interrupt
  302
- Waveform for Master Transmitter Transitioning to Master Receiver
  302
- Setting up a Transition from Slave Receiver to Slave Transmitter
  303
- Pre-Configuring
  303
- Setting up the First Interrupt
  303
- Setting up the Second Interrupt
  304
- Setting up the Third Interrupt
  304
- Waveform for Slave Receiver Transitioning to Slave Transmitter
  304
- I 2 C Bus Interface Registers
  305
- STA and STO Settings
  305
14 Counter

308
- Description
  308
- Block Diagram
  308
- H Counter Operation
  308
- H Counter Block Diagram
  308
- H Counter Operation Example
  308
- H Counter Pins
  309
- H Counter Input Signal Timing
  309
- H Counter Control Registers
  311
Appendix A Register Map

313
- Register Map: X'007E00' to X'007Fff
  313
- Register Map: X'00Fc00' to X'00Fdff
  314
- Register Map: X'00Fe00' to X'00Ffff
  315
- B.1 Description
  317
Appendix B MN102HF75K Flash EEPROM Version

317

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