Pioneer HD-V9000 Service Manual page 71
Hd video system
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Also See for HD-V9000:
- Specification sheet (2 pages) ,
- Operating instructions manual (152 pages) ,
- Technical manual (27 pages)
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5
QQ
3 7 63 1515 0
A
8/18
8:3B
FPGA_SCALER
SCALER IF
TE
L 13942296513
V C C O _ T O P 3
I O _ L 2 7 N _ 0
C1502
I O _ L 2 7 P _ 0
0-4TQG144C
I O _ L 3 0 N _ 0
I O _ L 3 0 P _ 0
I O _ L 3 1 N _ 0
FPGA
I O _ L 3 1 P _ 0 / V R E F _ 0
I O _ L 3 2 N _ 0 / G C L K 7
I O _ L 3 2 P _ 0 / G C L K 6
V C C O _ T O P 2
/VIDEO STREAM I/F
I O _ L 3 2 N _ 1 / G C L K 5
O LEVEL CONVERTER
I O _ L 3 2 P _ 1 / G C L K 4
I O _ L 3 1 N _ 1 / V R E F _ 1
ACCESS CONTROLLER
I O _ L 3 1 P _ 1
I O _ L 2 8 N _ 1
I O _ L 2 8 P _ 1
V C C O _ T O P 1
www
.
5
http://www.xiaoyu163.com
V+3R3D_1F_IC
R 1 5 9 3
1 0 k
N M
C 1 5 3 4
GNDD
12J
TP1600
F P G A _ J T A G _ T D I
JTAG IF
1 4 4
T D I
1 4 3
TP1618
P R O G _ B
(AD)
R 1 5 6 3
1 4 2
H S W A P _ E N
1 4 1
0
TP1607
1 4 0
TP1620
1 3 9
G N D 1 6
C 1 5 2 6
1 3 8
0 . 1 u / 1 0
1 3 7
TP1601
(AD)
1 3 6
G N D 1 5
1 3 5
TP1602
C 1 5 2 4
1 3 4
0 . 1 u / 1 0
V C C A U X 4
1 3 3
TP1621
V C C I N T 4
C 1 5 2 2
1 3 2
0 . 1 u / 1 0
1 3 1
TP1606
1 3 0
TP1605
1 2 9
TP1604
TP1603
1 2 8
TP1622
1 2 7
C 1 5 2 7
1 2 6
0 . 1 u / 1 0
(AD)
1 2 5
TP1610
1 2 4
TP1609
1 2 3
TP1608
TP1611
1 2 2
C 1 5 2 3
1 2 1
0 . 1 u / 1 0
V C C I N T 3
C 1 5 2 5
1 2 0
0 . 1 u / 1 0
V C C A U X 3
1 1 9
TP1614
1 1 8
TP1613
1 1 7
G N D 1 4
TP1612
1 1 6
I O 2
1 1 5
C 1 5 2 8
1 1 4
0 . 1 u / 1 0
G N D 1 3
1 1 3
TP1616
1 1 2
TP1615
TP1599
1 1 1
T M S
TP1598
1 1 0
T C K
1 0 9
TP1617
TP1597
R 1 5 6 5
2 2
T D O
JTAG IF
V+3R3D_1F_IC
A
9/18
9:12H
TP1584
# I R Q _ L A N
from LAN
# I R Q _ M I N T
R 1 5 6 1
N M
to MainCPU
x
ao
A
7/18
y
7:6K
MINT_FPGA_BUS
i
V+3R3D_1F_IC
#INT_MINT
R 1 5 6 4
1 0 k
http://www.xiaoyu163.com
6
8
A
4/18
TP1625
R 1 5 6 6
0
R 1 5 6 7
0
Q Q
R 1 5 6 8
0
3
6 7
1 3
TP1619
R 1 5 6 9
#WE_SARADEC
0
TP1623
R 1 5 8 1
2 2
TP1624
R 1 5 8 2
2 2
TP1626
R 1 5 8 3
2 2
R 1 5 8 4
3 3
HOST_DATA1
R 1 5 8 5
3 3
HOST_DATA0
TP1644
R 1 5 7 0
VOCLK_FPGA
0
TP1645
R 1 5 7 1
0
R 1 5 7 2
0
TP1627
R 1 5 7 3
0
R 1 5 7 4
0
R 1 5 7 5
HOST_ADRS7
0
R 1 5 7 6
HOST_ADRS6
0
R 1 5 7 7
HOST_ADRS5
0
HOST_ADRS4
R 1 5 7 8
0
R 1 5 7 9
HOST_ADRS3
0
R 1 5 8 0
HOST_ADRS2
0
V+2R5D_F_IC
4 . 7 k
R 1 5 8 6
R 1 5 8 7
4 . 7 k
R 1 5 8 8
4 . 7 k
FPGA_JTAG_TCK
FPGA_JTAG_TDO
FPGA_JTAG_TMS
10E
F P G A _ J T A G _ T D I
NOTES
NM
is Standby
u163
RS1/16SS***J
RAB4CQ***J
GDC IF
.
CKSSYB***K
(RYB)
CKSRYB***K
(CH)
CCSSCH***J
***/**
CEHVAW***M**
HD-V9000
6
7
2 9
9 4
2 8
DECM SERVICE ASSY (DXX2610)
• FPGA BLOCK
(AD)
: Audio Data Signal Route
A
5/18
5:11K;5:13B;5:8A
FPGA_SARADEC
SARADEC IF
V+2R5D_F_IC
3V-2.5V Level Shifter
TC7SH08FUS1
O U T Y
G N D
4
3
I N A
2
V C C
I N B
5
1
IC1503
C 1 5 3 1
0 . 1 u / 1 0
GNDD
A
5/18
5:7L
FPGA_I2S
(AD)
ADATA
ALRCK
1 5
0 5
8
2 9
9 4
(AD)
10:8J;14:2C;15:2D
A U D _ A D A T A
10:8J;14:2C;15:2D
A U D _ B C K
10:8K;14:2C;15:2D
A U D _ L R C K
VOFSYNC
GNDD
GNDD
(AD)
ASCLK
11:15I
A C L K _ F P G A
from EXT.SYNC
10:11K
# I R Q _ H D M I
from HDMI
V+2R5D_F_IC
TP1632
GNDD
GNDD
C N 1 5 0 1
1
TP1628
R 1 5 8 9
N M
2
1
POWER
FPGA
TP1629
2
TCK
3
3
TDO
JTAG IF
TP1630
R 1 5 9 0
N M
4
TMS
4
5
TDI
PIN HEADER
TP1631
R 1 5 9 1
N M
6
GND
5
6
N M
GNDD
m
co
[
]
[
]
[F/V]
[F/V]
[F/V]
[F/V]
7
8
9 9
A
B
A
1/18
1:6L
P R O G _ B
CONFIG IF
from MainCPU
C
SARADEC I2S IF
2 8
9 9
to Audio Main
Audio Digi
HDMI
A
10,14,15/18
D
A
11/18
A
10/18
E
F
A
4/18
71
8
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