Technical data of CPU 31xC
6.2 CPU 312C
Technical data
Data areas and their retentivity
Flag bits
•
•
Clock flag bits
Data blocks
•
Local data per priority class
Blocks
Total
OBs
•
Nesting depth
•
•
FBs
•
•
FCs
•
•
Address areas (I/O)
Total I/O address area
I/O process image
Digital channels
•
•
Analog channels
•
•
Assembly
Racks
Modules per rack
Number of DP masters
•
•
6-4
Retentive address areas
Default retentivity
Size
Size
Per priority class
additional within an error OB
Number, Max.
Size
Number, Max.
Size
Of those central
Integrated channels
Of those central
Integrated channels
Integrated
Via CP
128 bytes
Configurable
MB0 to MB15
8 (1 byte per flag bit)
Max. 511
(in the 1 to 511 range of numbers)
Max. 16 KB
Max. 256 bytes
1024 (DBs, FCs, FBs)
The maximum number of blocks that can be
loaded may be reduced if you are using another
MMC.
see the Instruction List
Max. 16 KB
8
4
1024
(in the 0 to 2047 range of numbers)
Max. 16 KB
1024
(in the 0 to 2047 range of numbers)
Max. 16 KB
Max. 1024 bytes/1024 bytes
(can be freely addressed)
128 bytes/128 bytes
Max. 256
Max. 256
10 DI / 6 DO
Max. 64
Max. 64
None
Max. 1
Max. 8
None
4
CPU 31xC and CPU 31x, Technical Data
Manual, 01/2006 Edition, A5E00105475-06