Outline Of Functions - NEC 78K0 Series User Manual

1.7 Outline of Functions

Item
Internal Flash memory
memory (self-programming
Note 1
(bytes) supported)
Memory bank
High-speed RAM
Expansion RAM
Memory space
Main system High-speed system
clock clock
(oscillation
frequency)
Internal high-speed
oscillation clock
Subsystem clock
(oscillation frequency)
Internal low-speed oscillation clock
(for TMH1, WDT)
General-purpose registers
Minimum instruction execution time
Instruction set
I/O ports
Timers
Timer outputs
Clock output
Buzzer output
A/D converter
Notes 1. The internal flash memory capacity, internal high-speed RAM capacity, and internal expansion RAM
capacity can be changed using the internal memory size switching register (IMS) and the internal
expansion RAM size switching register (IXS).
2. Banks to be used can be changed using the bank select register (BANK).
30
CHAPTER 1 OUTLINE
µ µ
PD78F0531 PD78F0532
16 K 24 K
Note 2
Note 1
768 1 K
−
Note 1
64 KB
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
1 to 20 MHz: V = 4.0 to 5.5 V, 1 to 10 MHz: V
DD
1 to 5 MHz: V = 1.8 to 5.5 V
DD
Internal oscillation
8 MHz (TYP.): V = 1.8 to 5.5 V
DD
XT1 (crystal) oscillation, external subsystem clock input (EXCLKS)
32.768 kHz (TYP.): V
DD
Internal oscillation
240 kHz (TYP.): V = 1.8 to 5.5 V
DD
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
µ
0.1 s (high-speed system clock: @ f
µ
0.25 s (TYP.) (internal high-speed oscillation clock: @ f
µ
122 s (subsystem clock: @ f
• 8-bit operation, 16-bit operation
• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)
• Bit manipulate (set, reset, test, and Boolean operation)
Total:
CMOS I/O:
CMOS output:
N-ch open-drain I/O (6 V tolerance): 4
• 16-bit timer/event counter: 1
channel
• 8-bit timer/event counter: 2
channels
• 8-bit timer: 2 channels
• Watch timer: 1 channel
• Watchdog timer: 1 channel
5 (PWM output: 4, PPG output: 1) 6 (PWM output: 4, PPG output: 2)
• 156.25 kHz, 312.5 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(peripheral hardware clock: @ f
• 32.768 kHz (subsystem clock: @ f
2.44 kHz, 4.88 kHz, 9.77 kHz, 19.54 kHz
(peripheral hardware clock: @ f
10-bit resolution × 8 channels (AV
Preliminary User's Manual U17260EJ3V1UD
µ µ µ
PD78F0533 PD78F0534 PD78F0535
32 K 48 K 60 K
−
1 K 2 K
= 2.7 to 5.5 V,
DD
= 1.8 to 5.5 V
= 20 MHz operation)
XH
= 32.768 kHz operation)
SUB
55
50
1
• 16-bit timer/event counter: 2 channels
• 8-bit timer/event counter: 2 channels
• 8-bit timer: 2 channels
• Watch timer: 1 channel
• Watchdog timer: 1 channel
= 20 MHz operation)
PRS
= 32.768 kHz operation)
SUB
= 20 MHz operation)
PRS
= 2.3 to 5.5 V)
REF
µ µ µ
PD78F0536 PD78F0537 PD78F0537D
96 K 128 K
4 6
4 K 6 K
= 8 MHz (TYP.) operation)
RH
• BCD adjust, etc.
(1/2)