(6) Main clock mode register (MCM)
This register selects the main system clock supplied to CPU clock and clock supplied to peripheral hardware
clock.
MCM can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Address: FFA1H
After reset: 00H
Symbol
7
MCM
0
XSEL
0
0
1
1
MCS
0
1
Note Bit 1 is read-only.
Cautions 1. XSEL can be changed only once after a reset release.
CHAPTER 6 CLOCK GENERATOR
Figure 6-6. Format of Main Clock Mode Register (MCM)
Note
R/W
6
5
0
0
MCM0
Selection of clock supplied to main system clock and peripheral hardware
Main system clock (f
0
Internal high-speed oscillation clock
(f
)
RH
1
0
1
High-speed system clock (f
Operates with internal high-speed oscillation clock
Operates with high-speed system clock
2. A clock other than f
regardless of the setting of XSEL and MCM0.
• Watchdog timer (operates with internal low-speed oscillation clock)
• When "f
7
", "f
/2
", or "f
RL
RL
(operates with internal low-speed oscillation clock)
• Peripheral hardware selects the external clock as the clock source
(Except when the external count clock of TM0n (n = 0, 1) is selected (TI00n pin
valid edge))
Preliminary User's Manual U17260EJ3V1UD
4
3
<2>
0
0
XSEL
)
Peripheral hardware clock (f
XP
Internal high-speed oscillation clock
(f
)
RH
High-speed system clock (f
)
XH
Main system clock status
is supplied to the following peripheral functions
PRS
9
/2
" is selected as the count clock for 8-bit timer H1
RL
<1>
<0>
MCS
MCM0
)
PRS
)
XH
143