Program And Data Memory; Sram Bank 0; Sram Bank 1; Schematic Diagram Of The External Cs0 Memory Interface - Motorola 56F8346 User Manual

2.2 Program and Data Memory

The 56F8346EVM contains two 128Kx16-bit Fast Static RAM banks. SRAM bank 0 is
controlled by CS0 and SRAM bank 1 is controlled by CS1 and CS2. This provides a total
of 256Kx16-bit of external memory.

2.2.1 SRAM Bank 0

SRAM bank 0, which is controlled by CS0, uses a 128K×16-bit Fast Static RAM (GSI
GS72116, labeled U2) for external memory expansion; see the FSRAM schematic
diagram in Figure 2-1. CS0 can be configured to use this memory bank as 16-bit program
memory, data memory, or both. Additionally, CS0 can be configured to assign this
memory's size and starting address to any modulo address space.
This memory bank will operate with zero wait state access while the 56F8346 is running at
60MHz and can be disabled by removing the jumper at JG5.
Figure 2-1. Schematic Diagram of the External CS0 Memory Interface

2.2.2 SRAM Bank 1

SRAM bank 1, which is controlled by CS1 and CS2, uses a 128K×16-bit Fast Static RAM
(GSI GS72116, labeled U3) for external memory expansion; see the FSRAM schematic
diagram in Figure 2-2. Using CS1 and CS2, this memory bank can be configured as byte
(8-bit) or word (16-bit) accessable program memory, data memory, or both. Additionally,
CS1 and CS2 can be configured to assign this memory's size and starting address to any
modulo address space.
2-4
Freescale Semiconductor, Inc.
56F8346
A0-A16
D0-D15
RD
WR
PS/CS0
Jumper Pin 1-2:
Enable SRAM
Jumper Removed:
Disable SRAM
56F8346EVM User Manual
For More Information On This Product,
Go to: www.freescale.com
GS72116
A0-A16
DQ0-DQ15
OE
WE
+3.3V
JG5
CE
MOTOROLA