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2 . 3 . 2
CPU Reads
A read operation is basically the same as a write operation. Reads are performed in word units.
2 . 3 . 3
DMA Writes
The DMA controller can perform display list, binary source, and delta YUV data transfers using
cycle stealing. To perform data transfer with the DMA controller, DMA mode settings must be
made in the DMA transfer start address register (DMASR), DMA transfer word count register
(DMAWR), and system control register (SYSR). After the DMA mode settings are made, the Q2
drives the DREQ signal low as soon as its preparations are completed. On receiving this signal,
the DMA controller reads data from memory and places it on the data bus. The data on the data bus
is then latched internally by the Q2 on the rise of the RD signal, and transferred to the UGM.
When DMA writes are performed using a display list or binary source as the data, the DMA mode
is set to 01. When DMA writes are performed using YUV data as the data, the DMA mode is set
to 11.
The Q2 accepts data in word units.
In DMA mode, the Q2 does not output hardware waits to the CPU.
For the DMA mode, set cycle-steal DMA mode edge detection and single address mode.
When an SH704X (SH-2) is used as the CPU, a setting must be made to enable extension of the
CPU's CS assertion period.
UGM access by the CPU should not be performed if the DMA mode setting is 01 or 11.
2 . 3 . 4
Interrupts
The Q2 interrupts the CPU by means of seven Q2 internal sources. Interrupt sources are set in the
interrupt enable register (IER).
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