Table of Contents
Advertisement
Schematic Notes
Model 11848 A
Table 8. Schematic Diagram Notes (9 of 11)
AND GATE
A-
B-
OR GATE
EXCLUSIVE-OR
GATE
I~~A
H
H
L
L
B
H
L
H
L
r~*
H
L
L
L
[ A
H
H
L
L
B
H
L
H
L
Hx
H
H
H
L
=1
r~*
H
H
L
L
B
H
L
H
L
~x
L
H
H
L
OPEN COLLECTOR
OUTPUTS (TTL)
+v
INPUTS
NAND GATE
A-
B-
OR GATE WITH
INVERTED INPUTS
A-
n*
H
H
L
L
B
H
L
H
L
r~x
L
H
H
H
^1
EXTERNAL
PULL-UP
RESISTOR
NOR GATE
A-
B-
^1
AND GATE WITH
INVERTED INPUTS
A-
B-
>
BUFFER
INVERTER
OPEN EMITTER
OUTPUTS (ECL)
INPUTS
1
A
H
H
L
L
j
B
H
L
H
L
~ X
|
L
L
L
H
\ A
H
L
~ ~ *
H
L
f A
H
L
~~X
L
H
EXTERNAL
PULL-DOWN
RESISTOR
- V
86
Advertisement
Table of Contents
