Iii) Timer Compare Force Register; Iv) Input Capture - Motorola 68HC12 User Manual

Timer Compare Force Register
This is a special register that allows the programmer to cause an output compare to
trigger. Writing to bit n in this register causes the action which is programmed
for output compare n to occur immediately.
comparison had just taken place with the TCn register.
_H12CFORC:
bit 7 bit 6
FOC7 FOC6
Input Capture
The operation of the input capture is similar to that of the output compare.
first step is to set up the appropriate Port T bits as input capture pins using
_H12TIOS.
Having done that, it is then necessary to select how the input capture will be
triggered. This is done using _H12TCTL3 and _H12TCTL4.
control bits EDGxB and EDGxA, which determine which edge triggers the input
capture. The different configurations of these bits are in Table 5.
Table 5: Input Capture selects
EDGxB EDGxA
0 0
0 1
1 0
1 1
_H12TCTL3:
bit 7 bit 6
EDG7B EDG7A
_H12TCTL4:
bit 7 bit 6
EDG3B EDG3A
Just as with the output compare operation, the timer interrupts must be disabled
and the timer module must be enabled.
capture are stored in the appropriate _H12TCx register.
Sample Code
This code captures the time of _H12TCNT when a switch is pressed by the user.
_H12TMSK1=0x00;
_H12TIOS=0x00;
_H12TCTL3=0x5A;
_H12TCTL4=0x5F;
_H12TSCR=0x80;
bit 5 bit 4
FOC5 FOC4
Configuration__________
Capture disabled
Capture on rising edge
Capture on falling edge
Capture on any edge.
bit 5 bit 4
EDG6B EDG6A
bit 5 bit 4
EDG2B EDG2A
// turn off interrupts
// Set up Port T for input capture
// IC7, IC6 rising edge, IC5, IC4 falling edge
// IC3, IC2 rising edge, IC1, IC0 any edge
// turn on the timer
This is the same as if a successful
bit 3 bit 2
FOC3 FOC2
bit 3 bit 2
EDG5B EDG5A
bit 3 bit 2
EDG1B EDG1A
The values that are read in by the input
15
bit 1 bit 0
FOC1 FOC0
Each channel has two
bit 1 bit 0
EDG4B EDG4A
bit 1 bit 0
EDG0B EDG0A
The