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In this chapter the ADS block diagram is described in detail.
5•1
Reset & Reset - Configuration
There are available reset sources on the MSC8101ADS:
1)
Power-On-Reset and manual
2)
Manual Hard-Reset
3)
Manual Soft-Reset
4)
JTAG/ONCE - Reset
5)
MSC8101 internal Resets. See [4].
5•1•1
Power- On Reset
The power on reset to the MSC8101ADS initializes the processor state after power up. A dedicated
logic, using Seiko S-80808AN, which is a voltage detector of 1.0V +/- 2.0% keeps nominal core
power supplying. Its open-drain output scheme allows off-board RESET sources e.g. pulse gener-
ator. PORESET is asserted to the MSC8101ADS for a period of ~300 msec and keeps.This time
period is long enough to cover also the Core and I/O supply stabilization, powered by a different
voltage regulator. Power-On-Reset may be generated manually as well by a dedicated push-
button.
5•1•1•1
Power - On Reset Configuration
At the end of Power - On reset sequence, MODCK(1:3) are sampled by the MSC8101 and together
with two additional clock configuration bits and set the various clock modes of the MSC8101
system (dsp core, cpm, 60x bus). Selection between the MODCK(1:3) combination options is done
by means of DIP-switches. See
Following Power-on reset sequence is the hard-reset sequence, within which, many other different
options are configured (see
bits are sampled at hard-reset configuration, whenever hard-reset sequence is entered, they are
influential only once - after power-on reset. If a hard reset sequence is entered later on, these bits
although sampled, are don't care.
5•1•2
Manual Hard Reset
To allow run-time Hard-reset, when the Command Converter is disconnected from the
MSC8101ADS and to support resident debuggers, manual Hard is facilitated. Depressing both
Soft-Reset and ABORT buttons asserts the HRESET pin of the MSC8101, generating a HARD
RESET sequence.
Since the HRESET line may be driven internally by the MSC8101, it must be driven to the
MSC8101 with an open-drain gate. If off-board H/W connected to the MSC8101ADS is to drive
HRESET line, then it should do so with an open-drain gate, this, to avoid contention over this line.
When Hard Reset is generated, the MSC8101 is reset in a destructive manner, i.e., the hard reset
configuration is re-sampled and all registers (except for the PLL's) are reset, including memory
controller registers - reset of which results in a loss of dynamic memory contents.
To save on board's real-estate, this button is not a dedicated one, but is shared with the Soft-Reset
button and the ABORT button - when both are depressed, Hard Reset is generated. The Soft
Reset is action achieved by using one dedicated button and provides DSP core reset only as well
as JTAG reset without sampling reset configuration word.
5•1•3
Hard Reset Configuration
When Hard-Reset is applied to the MSC8101ADS (externally as well as internally), it samples the
MOTOROLA
Freescale Semiconductor, Inc.
Functional Description
5 - Functional Description
TABLE 4-1. "Available Clock Mode Setting" on page
TABLE 5-2. "Hard Reset Configuration Word" on page
MSC8101ADS RevB User's Manual
For More Information On This Product,
Go to: www.freescale.com
29.
40). MODCKs
39
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