Motorola MSC8101 ADS User Manual page 37

TABLE 4-4. Memory Controller Initialization for 100(50)
Reg. Device Type
BR5 PM5350 - ATM UNI
OR5
BR6 User's peripheral
OR6
BR7 User's peripheral
OR7
BR10 DSPRAM
OR10
BR11 DSP Peripherals
OR11
PSDMR SDRAM 64bit
SDRAM 32bit
PSRT SDRAM Supported
MPTPR SDRAM Supported
MOTOROLA
Freescale Semiconductor, Inc.
Operating Instructions
Init Value
Bus
[hex]
Buffered 14600801
PPC
FFFF8E36
Buffered -
PPC
-
Buffered -
PPC
-
Local PPC 020000C1
FFF80000
Local PPC 01F00021
FFFF0000
Non-buffered C26B36A3
PPC (C2692452)
Non-buffered C28737A3
PPC with (C2432552)
Host support
22
All PPC Bus
Config.
2800(1300)
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a
MHz
Description
Base at 14600000, 8 bit port size, no parity, GPCM
on PPC bus.
32K Byte block size, delayed CS assertion, early
CS and WE negation for write cycle, relaxed
timing, 7 w.s. for read, 8 for write, extended hold
time after read.
-
-
-
-
Base at 200000, 64 bit port size, no parity,UPMC
512K Byte block size
Base at 1F00000, 64 bit port size, no parity, GPCM
on local PPC bus.
64K Byte block size
Page interleaving, Refresh enabled, normal
operation, address muxing mode SDAM=2, A(15-
17) on BNKSEL(0:2), A8 on PSDA10, 8(4) clocks
refresh recovery, 3(2) clocks precharge to activate
delay, 3(2) clocks activate to read/write delay, 4
beat burst length, 2(1) clock last data out to
precharge, 2(1) clock write recovery time, Internal
address muxing, normal timing, 3(2) clocks CAS
latency.
Page interleaving, Refresh enabled, normal
operation, address muxing mode 1, A(13-15) on
BNKSEL(0:2), A9 on PSDA10, 8(4) clocks refresh
recovery, 3(2) clocks precharge to activate delay,
3(2) clocks activate to read/write delay, 8 beat
burst length, 2(1) clock last data out to precharge,
2(1) clock write recovery time, Internal address
muxing, normal timing, 3(2) clocks CAS latency.
Generates refresh every 14 µsec, while 15.6 µsec
required. Therefore is refresh redundancy of 6.6
msec throughout full SDRAM refresh cycle which
completes in 64 msec. I.e., Application s/w may
withhold the bus upto app. 6.6 msec in a 57.3
msec period, without jeopardizing the contents of
the PPC bus SDRAM.
Divide Bus clock by 40D (20D)
37