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2.13
CACHE USE SCENARIO
This section demonstrates a possible scenario of cache use in a real time system.
1. The DSP96002 leaves the hardware reset in PRAM mode as determined by the mode
bits in the OMR.
2. To achieve "hit on first access" (especially important for the fast interrupt vectors), the
user, while still in PRAM mode and using DMA, transfers the interrupt vectors and
some critical routines into the lower PRAM addresses. The DMA transfers set the cor-
responding valid-bits. Presume that the code uses 200 PRAM words and therefore it
will be contained in 2 cache sectors. Since these routines are time critical, the user will
wish to lock the sectors. A possible code may look like this:
LABEL
user_code
3. To enter cache mode, the user sets OMR bit 4. To lock address 0 to 200 in the cache
the user issues the PLOCK instruction twice, each time with an effective address that
belongs to the corresponding memory sector. Please notice that three cycles should
separate the change of OMR bit 4 from the PLOCK instruction.
The code may look like this:
16
ADDRESS
CODE
$00000000
reset vector
. . .
$0000003e
host b write p memory vector
$00000040
user critical routines
. . .
$0000007f
end of sector 1
$00000080
beginning of sector 2
. . .
$000000c8
end of user critical routines
ORI #$10, OMR
NOP
NOP
NOP
PLOCK #0
MOVE #128, R0
NOP
PLOCK R0
; set CE bit in OMR
; pipeline delay
; pipeline delay
; pipeline delay
; lock sector containing address 0
; load effective address to r0
; pipeline delay for move
; lock sector containing address 128
MOTOROLA
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