Instruction Cache - Motorola DSP96002 User Manual

CONTROL
19 BUS
CONTROL
EXTERNAL
ADDRESS
ADDRESS
SWITCH
4
32-BIT HOST
INTERFACE
TIMER
EXTERNAL
DATA BUS
32
SWITCH
DATA
CLOCK
GENERATOR
CLK
stated during hardware reset, requires a weak external pull-up resistor, and can be con-
nected directly to the WE pin of a static RAM. The DSP96002 diagram shown in Figure 6
on page 29 includes the new write strobe pins.
The timings and functionality of TS and R/W remain unchanged, so that existing configu-
rations may still be used. From a logical standpoint, WR = (TS or R/W).

2 INSTRUCTION CACHE

2.1 INTRODUCTION
The instruction cache may be viewed as a buffer memory between the main (external
and probably slow) memory, and the fast CPU. The cache is used to store frequently
used program instructions and it offers an increase in throughput by eliminating the time
required to access the instruction words on the external bus.
Reduced external bus activity maintains single-cycle program memory access, while al-
lowing the use of a low cost, slow external program memory. It also frees the processor's
memory expansion port for other tasks such as data moves, DMA transfers, Host Interface
data moves, etc.
MOTOROLA
ADDRESS
GENERATION
UNIT (AGU)
DUAL CHANNEL
PROGRAM
DMA
MEMORY
CONTROLLER
1024x32
BOOTSTRAP
INTERNAL
INSTRUCTION
SWITCH and BIT
MANIPULATION
UNIT
PROGRAM PROGRAM
ADDRESS ADDRESS
GENERATOR GENERATOR
PROGRAM CONTROLLER
Figure 1 - DSP96002 Block Diagram
*
YAB
*
XAB
PAB *
*
*
Y DATA
X DATA
MEMORY
MEMORY
512x32
512x32
RAM
RAM
RAM
and
64x32
512x32
512x32
ROM
ROM
ROM
CACHE
DDB
YDB
XDB
PDB
GDB
PROGRAM
DATA ALU
INTERRUPT
CONTROLLER
• IEEE FLOATING POINT
• 32x32 INTEGER ALU
MODC/IRQC
MODB/IRQB
MODA/IRQA
RESET
CONTROL
BUS 19
CONTROL
EXTERNAL
ADDRESS
ADDRESS
SWITCH
4
*
32-BIT HOST
INTERFACE
TIMER
EXTERNAL
DATA BUS
32
SWITCH
DATA
OnCE DEBUG
CONTROLLER
SERIAL
4
DEBUG
PORT
32-BIT BUSES
DUAL ACCESS (DMA/CORE)
*
3