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Transition Module Preparation and Installation
Table 5-12 Multiplexing Sequence of the IOMX Function (continued)
MXDO
(From CPCI-6115 SBC)
Time Slot
4
5
6
7
8
9
10
11
12
13
14
15
MXSYNC# is clocked out using the falling edge of MXCLK and MDXO is clocked out with the
rising edge of the MXCLK. MXDI is sampled at the rising edge of MXCLK (the CPCI-6115-
MCPTM synchronizes MXDI with MXCLK's rising edge). The timing relationships among
MXCLK, MXSYNC#, MXDO, and MXDI are illustrated by the following figure:
Figure 5-6
Serial Port Signal Descriptions
CTSn
DCDn
DSRn
DTRn
106
Signal Name
RTS4
DTR4
Reserved
Reserved
Reserved
DTR1
DTR2
Reserved
Reserved
Reserved
Reserved
Reserved
P2MX Signal Timings
clear to send
data carrier detected
data set ready
data terminal ready
CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)
Asynchronous Serial Ports
MXDI
(From CPCI-6115-MCPTM or CPCI-6106)
Time Slot
Signal Name
4
RI3
5
CTS4
6
DSR4
7
DCD4
8
CTS2
9
RI4
10
RI1
11
DSR1
12
DCD1
13
RI2
14
DSR2
15
DCD2
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