ST RM0090 Manuals
Manuals and User Guides for ST RM0090. We have 1 ST RM0090 manual available for free PDF download: Reference Manual
ST RM0090 Reference Manual (1422 pages)
Brand: ST
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Category: Microcontrollers
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Size: 15.05 MB
Table of Contents
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Glossary48
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S0: I-Bus51
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S1: D-Bus51
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S2: S-Bus51
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Busmatrix51
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Memory Map52
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Bit Banding55
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Introduction59
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Erase66
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Programming67
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Interrupts68
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Option Bytes68
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Sleep Mode98
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Stop Mode99
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Standby Mode101
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PWR Register Map109
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Reset111
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System Reset111
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Power Reset112
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Clocks113
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HSE Clock116
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HSI Clock117
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LSE Clock118
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LSI Clock118
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RTC/AWU Clock119
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Watchdog Clock120
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RCC Registers123
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RCC Register Map181
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Port Pins196
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GPIO Registers198
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(X = a199
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(X = a201
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(X = a203
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SYSCFG Registers206
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(Syscfg_Exticr1)208
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(Syscfg_Exticr2)209
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(Syscfg_Exticr3)209
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(Syscfg_Exticr4)210
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DMA Introduction213
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DMA Transactions217
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Arbiter219
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DMA Streams220
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Circular Mode224
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Fifo227
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Flow Controller231
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Error Management234
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DMA Interrupts235
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DMA Registers235
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DMA Register Map245
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NVIC Features249
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EXTI Registers260
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ADC Introduction264
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ADC Clock266
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Timing Diagram268
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Analog Watchdog268
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Scan Mode269
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Data Alignment272
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Data Management276
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Using the DMA276
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Multi ADC Mode277
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Interleaved Mode283
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ADC Interrupts290
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ADC Registers291
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(Adc_Cdr)307
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DAC Introduction310
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DAC Data Format312
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DAC Conversion313
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DMA Request314
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Noise Generation315
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DAC Registers321
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(Dac_Dhr12R1)324
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(Dac_Dhr12L1)325
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(Dac_Dhr8R1)325
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(Dac_Dhr12R2)325
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(Dac_Dhr12L2)326
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(Dac_Dhr8R2)326
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(Dac_Dhr12Ld)327
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(Dac_Dhr8Rd)327
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DAC Register Map329
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DCMI Pins330
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DCMI Clocks330
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DMA Interface332
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Synchronization334
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Capture Modes336
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Crop Feature337
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JPEG Format338
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Fifo338
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Data Formats339
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RGB Format339
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Ycbcr Format340
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DCMI Interrupts340
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Time-Base Unit356
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Counter Modes357
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Clock Selection367
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PWM Input Mode372
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PWM Mode375
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One-Pulse Mode384
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Debug Mode393
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Time-Base Unit423
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Counter Modes425
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Clock Selection434
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PWM Input Mode439
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PWM Mode442
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One-Pulse Mode445
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Debug Mode458
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Time-Base Unit485
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Counter Modes486
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Clock Selection489
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PWM Mode496
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One-Pulse Mode497
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Debug Mode501
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(Timx_Ccmr1)519
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(Timx_Ccer)521
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Time-Base Unit526
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Counting Mode527
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Clock Source530
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Debug Mode530
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Debug Mode537
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IWDG Registers537
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Debug Mode544
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WWDG Registers545
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Data Type567
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CRYP Busy State571
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Context Swapping573
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CRYP Interrupts575
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CRYP Registers576
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RNG Introduction594
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Operation595
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Error Management595
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RNG Registers595
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RNG Register Map598
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Data Type602
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Message Padding605
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Hash Operation606
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HMAC Operation606
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Context Swapping607
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HASH Interrupt609
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HASH Registers609
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Introduction625
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Tamper Detection638
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Alarm Output640
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RTC Interrupts640
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RTC Registers642
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(Rtc_Tafcr)658
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RTC Register Map662
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Tx Mailboxes666
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Normal Mode668
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Test Mode669
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Silent Mode669
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Loop Back Mode670
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Debug Mode671
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Message Storage678
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Error Management680
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Bit Timing680
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Bxcan Interrupts683
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CAN Registers684
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Mode Selection709
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I2C Slave Mode711
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I2C Master Mode714
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Error Conditions719
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Smbus721
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DMA Requests724
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I 2 C Interrupts726
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I 2 C Debug Mode728
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I 2 C Registers728
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I2C Register Map741
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Transmitter747
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Receiver750
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Parity Control767
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Smartcard773
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USART Interrupts781
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USART Registers782
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SPI Introduction794
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SPI Features795
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I 2 S Features796
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CRC Calculation812
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Status Flags814
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Error Flags818
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SPI Interrupts819
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I2S Full Duplex821
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Clock Generator828
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I 2 S Slave Mode832
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Status Flags834
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Error Flags835
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I 2 S Interrupts836
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DMA Features836
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Table 126. I836
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Mode)841
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Mode)842
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SPI Register Map845
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SDIO Adapter850
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Card Reset861
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Block Write863
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Block Read863
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SD I/O Mode876
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Response Formats880
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R1B881
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R4 (Fast I/O)882
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R4B882
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SDIO Interrupts885
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CE-ATA Interrupt886
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Aborting CMD61886
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HW Flow Control886
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SDIO Registers887
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SDIO Response 1891
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DMA Features905
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PTP Features905
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Ethernet Pins906
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MAC Interrupts930
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MAC Filtering931
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DMA Arbiter947
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DMA Interrupts970
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OTG_FS Introduction1021
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OTG_FS Main Features1022
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General Features1022
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Host-Mode Features1023
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OTG Full-Speed Core1024
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Full-Speed OTG PHY1025
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ID Line Detection1026
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HNP Dual Role Device1026
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SRP Dual Role Device1027
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USB Peripheral1027
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Peripheral States1028
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Peripheral Endpoints1029
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USB Host1031
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SRP-Capable Host1032
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USB Host States1032
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Host Channels1034
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Host Scheduler1035
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SOF Trigger1036
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Host Sofs1036
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Peripheral Sofs1037
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Power Options1037
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USB Data Fifos1039
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Peripheral Rx FIFO1039
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Peripheral Tx Fifos1040
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Host Rx FIFO1040
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Host Tx Fifos1041
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FIFO RAM Allocation1041
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Device Mode1041
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Host Mode1042
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OTG_FS Interrupts1043
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CSR Memory Map1045
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Host-Mode Registers1072
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(Otg_Fs_Pcgcctl)1105
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OTG_FS Register Map1106
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Core Initialization1113
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Host Initialization1114
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Operational Model1134
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OTG_HS Introduction1159
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OTG_HS Main Features1160
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General Features1160
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Host-Mode Features1161
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High-Speed OTG PHY1162
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OTG Dual-Role Device1163
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ID Line Detection1163
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HNP Dual Role Device1163
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SRP Dual-Role Device1163
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Peripheral States1164
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Peripheral Endpoints1165
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SRP-Capable Host1168
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USB Host States1168
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Host Channels1170
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Host Scheduler1171
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SOF Trigger1172
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Host Sofs1172
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Peripheral Sofs1173
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USB_HS Power Modes1174
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FIFO RAM Allocation1175
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Peripheral Mode1175
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Host Mode1175
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OTG_HS Interrupts1176
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CSR Memory Map1179
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Host-Mode Registers1208
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(Otg_Hs_Pcgcctl)1247
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OTG_HS Register Map1248
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Core Initialization1260
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Host Initialization1261
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DMA Mode1262
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Mode1268
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Operational Model1292
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FSMC Main Features1317
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Block Diagram1318
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AHB Interface1319
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General Timing Rules1326
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FSMC Register Map1373
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Debug Support (DBG)1375
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Overview1375
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SWJ Debug Port Pins1378
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MCU Device ID Code1382
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Boundary Scan TAP1382
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Cortex™-M4F TAP1382
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JTAG Debug Port1383
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SW Debug Port1385
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SW Protocol Sequence1385
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SW-DP Registers1387
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SW-AP Registers1388
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Core Debug1390
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General Description1392
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General Description1394
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Main ETM Registers1395
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13961396
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Introduction1400
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TRACE Pin Assignment1401
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TPUI Formatter1402
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Synchronous Mode1403
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Asynchronous Mode1404
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TPIU Registers1405
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DBG Register Map1406
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Flash Size1408
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Revision History1413
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